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add fp load patterns, switch rest of loads and stores to use addrmodes

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24786 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-17 20:32:47 +00:00
parent 1963783fab
commit b575baf57d
2 changed files with 56 additions and 60 deletions
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58
lib/Target/Sparc/SparcInstrInfo.td
View File

@@ -156,23 +156,21 @@ def LDDri : F3_2<3, 0b000011,
// Section B.2 - Load Floating-point Instructions, p. 92 // Section B.2 - Load Floating-point Instructions, p. 92
def LDFrr : F3_1<3, 0b100000, def LDFrr : F3_1<3, 0b100000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops FPRegs:$dst, MEMrr:$addr),
"ld [$b+$c], $dst", []>; "ld [$addr], $dst",
[(set FPRegs:$dst, (load ADDRrr:$addr))]>;
def LDFri : F3_2<3, 0b100000, def LDFri : F3_2<3, 0b100000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c), (ops FPRegs:$dst, MEMri:$addr),
"ld [$b+$c], $dst", []>; "ld [$addr], $dst",
[(set FPRegs:$dst, (load ADDRri:$addr))]>;
def LDDFrr : F3_1<3, 0b100011, def LDDFrr : F3_1<3, 0b100011,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops DFPRegs:$dst, MEMrr:$addr),
"ldd [$b+$c], $dst", []>; "ldd [$addr], $dst",
[(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
def LDDFri : F3_2<3, 0b100011, def LDDFri : F3_2<3, 0b100011,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c), (ops DFPRegs:$dst, MEMri:$addr),
"ldd [$b+$c], $dst", []>; "ldd [$addr], $dst",
def LDFSRrr: F3_1<3, 0b100001, [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"ld [$b+$c], $dst", []>;
def LDFSRri: F3_2<3, 0b100001,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"ld [$b+$c], $dst", []>;
// Section B.4 - Store Integer Instructions, p. 95 // Section B.4 - Store Integer Instructions, p. 95
def STBri : F3_2<3, 0b000101, def STBri : F3_2<3, 0b000101,
@@ -190,29 +188,29 @@ def STDri : F3_2<3, 0b000111,
// Section B.5 - Store Floating-point Instructions, p. 97 // Section B.5 - Store Floating-point Instructions, p. 97
def STFrr : F3_1<3, 0b100100, def STFrr : F3_1<3, 0b100100,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STFri : F3_2<3, 0b100100, def STFri : F3_2<3, 0b100100,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STDFrr : F3_1<3, 0b100111, def STDFrr : F3_1<3, 0b100111,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
def STDFri : F3_2<3, 0b100111, def STDFri : F3_2<3, 0b100111,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
def STFSRrr : F3_1<3, 0b100101, def STFSRrr : F3_1<3, 0b100101,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STFSRri : F3_2<3, 0b100101, def STFSRri : F3_2<3, 0b100101,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STDFQrr : F3_1<3, 0b100110, def STDFQrr : F3_1<3, 0b100110,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
def STDFQri : F3_2<3, 0b100110, def STDFQri : F3_2<3, 0b100110,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
// Section B.9 - SETHI Instruction, p. 104 // Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100, def SETHIi: F2_1<0b100,

58
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@@ -156,23 +156,21 @@ def LDDri : F3_2<3, 0b000011,
// Section B.2 - Load Floating-point Instructions, p. 92 // Section B.2 - Load Floating-point Instructions, p. 92
def LDFrr : F3_1<3, 0b100000, def LDFrr : F3_1<3, 0b100000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops FPRegs:$dst, MEMrr:$addr),
"ld [$b+$c], $dst", []>; "ld [$addr], $dst",
[(set FPRegs:$dst, (load ADDRrr:$addr))]>;
def LDFri : F3_2<3, 0b100000, def LDFri : F3_2<3, 0b100000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c), (ops FPRegs:$dst, MEMri:$addr),
"ld [$b+$c], $dst", []>; "ld [$addr], $dst",
[(set FPRegs:$dst, (load ADDRri:$addr))]>;
def LDDFrr : F3_1<3, 0b100011, def LDDFrr : F3_1<3, 0b100011,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops DFPRegs:$dst, MEMrr:$addr),
"ldd [$b+$c], $dst", []>; "ldd [$addr], $dst",
[(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
def LDDFri : F3_2<3, 0b100011, def LDDFri : F3_2<3, 0b100011,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c), (ops DFPRegs:$dst, MEMri:$addr),
"ldd [$b+$c], $dst", []>; "ldd [$addr], $dst",
def LDFSRrr: F3_1<3, 0b100001, [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"ld [$b+$c], $dst", []>;
def LDFSRri: F3_2<3, 0b100001,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"ld [$b+$c], $dst", []>;
// Section B.4 - Store Integer Instructions, p. 95 // Section B.4 - Store Integer Instructions, p. 95
def STBri : F3_2<3, 0b000101, def STBri : F3_2<3, 0b000101,
@@ -190,29 +188,29 @@ def STDri : F3_2<3, 0b000111,
// Section B.5 - Store Floating-point Instructions, p. 97 // Section B.5 - Store Floating-point Instructions, p. 97
def STFrr : F3_1<3, 0b100100, def STFrr : F3_1<3, 0b100100,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STFri : F3_2<3, 0b100100, def STFri : F3_2<3, 0b100100,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STDFrr : F3_1<3, 0b100111, def STDFrr : F3_1<3, 0b100111,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
def STDFri : F3_2<3, 0b100111, def STDFri : F3_2<3, 0b100111,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
def STFSRrr : F3_1<3, 0b100101, def STFSRrr : F3_1<3, 0b100101,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STFSRri : F3_2<3, 0b100101, def STFSRri : F3_2<3, 0b100101,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"st $src, [$base+$offset]", []>; "st $src, [$addr]", []>;
def STDFQrr : F3_1<3, 0b100110, def STDFQrr : F3_1<3, 0b100110,
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src), (ops MEMrr:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
def STDFQri : F3_2<3, 0b100110, def STDFQri : F3_2<3, 0b100110,
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src), (ops MEMri:$addr, IntRegs:$src),
"std $src, [$base+$offset]", []>; "std $src, [$addr]", []>;
// Section B.9 - SETHI Instruction, p. 104 // Section B.9 - SETHI Instruction, p. 104
def SETHIi: F2_1<0b100, def SETHIi: F2_1<0b100,