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add fp load patterns, switch rest of loads and stores to use addrmodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24786 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -156,23 +156,21 @@ def LDDri : F3_2<3, 0b000011,
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst", []>;
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(ops FPRegs:$dst, MEMrr:$addr),
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"ld [$addr], $dst",
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[(set FPRegs:$dst, (load ADDRrr:$addr))]>;
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def LDFri : F3_2<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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(ops FPRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set FPRegs:$dst, (load ADDRri:$addr))]>;
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def LDDFrr : F3_1<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ldd [$b+$c], $dst", []>;
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(ops DFPRegs:$dst, MEMrr:$addr),
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"ldd [$addr], $dst",
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[(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
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def LDDFri : F3_2<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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def LDFSRrr: F3_1<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst", []>;
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def LDFSRri: F3_2<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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(ops DFPRegs:$dst, MEMri:$addr),
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"ldd [$addr], $dst",
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[(set DFPRegs:$dst, (load ADDRri:$addr))]>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBri : F3_2<3, 0b000101,
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@ -190,29 +188,29 @@ def STDri : F3_2<3, 0b000111,
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STFri : F3_2<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STDFrr : F3_1<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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def STDFri : F3_2<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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def STFSRrr : F3_1<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STFSRri : F3_2<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STDFQrr : F3_1<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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def STDFQri : F3_2<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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@ -156,23 +156,21 @@ def LDDri : F3_2<3, 0b000011,
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst", []>;
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(ops FPRegs:$dst, MEMrr:$addr),
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"ld [$addr], $dst",
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[(set FPRegs:$dst, (load ADDRrr:$addr))]>;
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def LDFri : F3_2<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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(ops FPRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set FPRegs:$dst, (load ADDRri:$addr))]>;
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def LDDFrr : F3_1<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ldd [$b+$c], $dst", []>;
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(ops DFPRegs:$dst, MEMrr:$addr),
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"ldd [$addr], $dst",
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[(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
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def LDDFri : F3_2<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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def LDFSRrr: F3_1<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst", []>;
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def LDFSRri: F3_2<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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(ops DFPRegs:$dst, MEMri:$addr),
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"ldd [$addr], $dst",
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[(set DFPRegs:$dst, (load ADDRri:$addr))]>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBri : F3_2<3, 0b000101,
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@ -190,29 +188,29 @@ def STDri : F3_2<3, 0b000111,
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STFri : F3_2<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STDFrr : F3_1<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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def STDFri : F3_2<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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def STFSRrr : F3_1<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STFSRri : F3_2<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]", []>;
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def STDFQrr : F3_1<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMrr:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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def STDFQri : F3_2<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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(ops MEMri:$addr, IntRegs:$src),
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"std $src, [$addr]", []>;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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