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Move the list of registers into CodeGenRegBank.

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Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-06-11 00:28:06 +00:00
parent 25255cbe00
commit b5923db192
5 changed files with 254 additions and 208 deletions
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utils/TableGen/CodeGenTarget.cpp
+1 -14
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@@ -163,19 +163,6 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
return *RegBank;
}
void CodeGenTarget::ReadRegisters() const {
std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
if (Regs.empty())
throw std::string("No 'Register' subclasses defined!");
std::sort(Regs.begin(), Regs.end(), LessRecord());
Registers.reserve(Regs.size());
Registers.assign(Regs.begin(), Regs.end());
// Assign the enumeration values.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Registers[i].EnumValue = i + 1;
}
void CodeGenTarget::ReadRegisterClasses() const {
std::vector<Record*> RegClasses =
Records.getAllDerivedDefinitions("RegisterClass");
@@ -189,7 +176,7 @@ void CodeGenTarget::ReadRegisterClasses() const {
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
const std::vector<CodeGenRegister> &Regs = getRegisters();
const std::vector<CodeGenRegister> &Regs = getRegBank().getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = Regs[i];
if (Reg.TheDef->getValueAsString("AsmName") == Name)