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Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24595 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -156,31 +156,31 @@ def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
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def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"mix1.l $dst = $src1, $src2;;",
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[(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
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(and (srl GR:$src2, 8), isMIX1Lable)))]>;
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(and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>;
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def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"mix2.l $dst = $src1, $src2;;",
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[(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
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(and (srl GR:$src2, 16), isMIX2Lable)))]>;
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(and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>;
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def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"mix4.l $dst = $src1, $src2;;",
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[(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
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(and (srl GR:$src2, 32), isMIX4Lable)))]>;
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(and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>;
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def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"mix1.r $dst = $src1, $src2;;",
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[(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable),
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[(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
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(and GR:$src2, isMIX1Rable)))]>;
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def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"mix2.r $dst = $src1, $src2;;",
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[(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable),
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[(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
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(and GR:$src2, isMIX2Rable)))]>;
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def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
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"mix4.r $dst = $src1, $src2;;",
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[(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
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[(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
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(and GR:$src2, isMIX4Rable)))]>;
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def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
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