6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2008-08-28 18:06:12 +00:00
parent 97efa36586
commit b5dbcb538b
1 changed files with 43 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
utils/TableGen/FastISelEmitter.cpp
View File

@ -172,6 +172,7 @@ struct OperandsSignature {
struct InstructionMemo {
std::string Name;
const CodeGenRegisterClass *RC;
unsigned char SubRegNo;
};
class FastISelMap {
@ -235,12 +236,19 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
// For now, ignore instructions where the first operand is not an
// output register.
Record *Op0Rec = II.OperandList[0].Rec;
if (!Op0Rec->isSubClassOf("RegisterClass"))
continue;
const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec);
if (!DstRC)
continue;
const CodeGenRegisterClass *DstRC = 0;
unsigned SubRegNo = ~0;
if (Op->getName() != "EXTRACT_SUBREG") {
Record *Op0Rec = II.OperandList[0].Rec;
if (!Op0Rec->isSubClassOf("RegisterClass"))
continue;
DstRC = &Target.getRegisterClass(Op0Rec);
if (!DstRC)
continue;
} else {
SubRegNo = static_cast<IntInit*>(
Dst->getChild(1)->getLeafValue())->getValue();
}
// Inspect the pattern.
TreePatternNode *InstPatNode = Pattern.getSrcPattern();
@ -274,7 +282,8 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
// Ok, we found a pattern that we can handle. Remember it.
InstructionMemo Memo = {
Pattern.getDstPattern()->getOperator()->getName(),
DstRC
DstRC,
SubRegNo
};
assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
"Duplicate pattern!");
@ -410,13 +419,19 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
HasPred = true;
}
OS << " return FastEmitInst_";
Operands.PrintManglingSuffix(OS);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
OS << ", ";
Operands.PrintArguments(OS);
OS << ");\n";
if (Memo.SubRegNo == (unsigned char)~0) {
Operands.PrintManglingSuffix(OS);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
OS << ", ";
Operands.PrintArguments(OS);
OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
}
// Return 0 if none of the predicates were satisfied.
if (HasPred)
@ -482,13 +497,20 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
HasPred = true;
}
OS << " return FastEmitInst_";
Operands.PrintManglingSuffix(OS);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
OS << ", ";
Operands.PrintArguments(OS);
OS << ");\n";
if (Memo.SubRegNo == (unsigned char)~0) {
Operands.PrintManglingSuffix(OS);
OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass";
if (!Operands.empty())
OS << ", ";
Operands.PrintArguments(OS);
OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
}
// Return 0 if none of the predicates were satisfied.