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Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2008-08-28 18:06:12 +00:00
parent 97efa36586
commit b5dbcb538b
1 changed files with 43 additions and 21 deletions
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26
utils/TableGen/FastISelEmitter.cpp
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@ -172,6 +172,7 @@ struct OperandsSignature {
struct InstructionMemo { struct InstructionMemo {
std::string Name; std::string Name;
const CodeGenRegisterClass *RC; const CodeGenRegisterClass *RC;
unsigned char SubRegNo;
}; };
class FastISelMap { class FastISelMap {
@ -235,12 +236,19 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
// For now, ignore instructions where the first operand is not an // For now, ignore instructions where the first operand is not an
// output register. // output register.
const CodeGenRegisterClass *DstRC = 0;
unsigned SubRegNo = ~0;
if (Op->getName() != "EXTRACT_SUBREG") {
Record *Op0Rec = II.OperandList[0].Rec; Record *Op0Rec = II.OperandList[0].Rec;
if (!Op0Rec->isSubClassOf("RegisterClass")) if (!Op0Rec->isSubClassOf("RegisterClass"))
continue; continue;
const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec); DstRC = &Target.getRegisterClass(Op0Rec);
if (!DstRC) if (!DstRC)
continue; continue;
} else {
SubRegNo = static_cast<IntInit*>(
Dst->getChild(1)->getLeafValue())->getValue();
}
// Inspect the pattern. // Inspect the pattern.
TreePatternNode *InstPatNode = Pattern.getSrcPattern(); TreePatternNode *InstPatNode = Pattern.getSrcPattern();
@ -274,7 +282,8 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
// Ok, we found a pattern that we can handle. Remember it. // Ok, we found a pattern that we can handle. Remember it.
InstructionMemo Memo = { InstructionMemo Memo = {
Pattern.getDstPattern()->getOperator()->getName(), Pattern.getDstPattern()->getOperator()->getName(),
DstRC DstRC,
SubRegNo
}; };
assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) && assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
"Duplicate pattern!"); "Duplicate pattern!");
@ -410,6 +419,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
HasPred = true; HasPred = true;
} }
OS << " return FastEmitInst_"; OS << " return FastEmitInst_";
if (Memo.SubRegNo == (unsigned char)~0) {
Operands.PrintManglingSuffix(OS); Operands.PrintManglingSuffix(OS);
OS << "(" << InstNS << Memo.Name << ", "; OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass"; OS << InstNS << Memo.RC->getName() << "RegisterClass";
@ -417,6 +427,11 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
OS << ", "; OS << ", ";
Operands.PrintArguments(OS); Operands.PrintArguments(OS);
OS << ");\n"; OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
} }
// Return 0 if none of the predicates were satisfied. // Return 0 if none of the predicates were satisfied.
if (HasPred) if (HasPred)
@ -482,6 +497,8 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
HasPred = true; HasPred = true;
} }
OS << " return FastEmitInst_"; OS << " return FastEmitInst_";
if (Memo.SubRegNo == (unsigned char)~0) {
Operands.PrintManglingSuffix(OS); Operands.PrintManglingSuffix(OS);
OS << "(" << InstNS << Memo.Name << ", "; OS << "(" << InstNS << Memo.Name << ", ";
OS << InstNS << Memo.RC->getName() << "RegisterClass"; OS << InstNS << Memo.RC->getName() << "RegisterClass";
@ -489,6 +506,11 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) {
OS << ", "; OS << ", ";
Operands.PrintArguments(OS); Operands.PrintArguments(OS);
OS << ");\n"; OS << ");\n";
} else {
OS << "extractsubreg(Op0, ";
OS << (unsigned)Memo.SubRegNo;
OS << ");\n";
}
} }
// Return 0 if none of the predicates were satisfied. // Return 0 if none of the predicates were satisfied.