mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Removed isPredicable().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
5ada199246
commit
b5f8eff566
@ -423,15 +423,6 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
|
||||
return false;
|
||||
}
|
||||
|
||||
bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const {
|
||||
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
|
||||
if (TID->Flags & M_PREDICATED)
|
||||
return true;
|
||||
|
||||
unsigned Opc = MI->getOpcode();
|
||||
return Opc == ARM::B || Opc == ARM::tB;
|
||||
}
|
||||
|
||||
void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Cond) const {
|
||||
unsigned Opc = MI->getOpcode();
|
||||
|
@ -104,7 +104,6 @@ public:
|
||||
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
||||
|
||||
// Predication support.
|
||||
virtual bool isPredicatable(MachineInstr *MI) const;
|
||||
virtual void PredicateInstruction(MachineInstr *MI,
|
||||
std::vector<MachineOperand> &Cond) const;
|
||||
};
|
||||
|
Loading…
Reference in New Issue
Block a user