mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
Add support for matching psign & plendvb to the x86 target
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122098 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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d715e07efe
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@ -981,6 +981,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRA);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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if (Subtarget->is64Bit())
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if (Subtarget->is64Bit())
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@ -8870,6 +8871,10 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::PINSRB: return "X86ISD::PINSRB";
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case X86ISD::PINSRB: return "X86ISD::PINSRB";
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case X86ISD::PINSRW: return "X86ISD::PINSRW";
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case X86ISD::PINSRW: return "X86ISD::PINSRW";
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case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
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case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
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case X86ISD::PANDN: return "X86ISD::PANDN";
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case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
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case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
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case X86ISD::PSIGND: return "X86ISD::PSIGND";
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case X86ISD::FMAX: return "X86ISD::FMAX";
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case X86ISD::FMAX: return "X86ISD::FMAX";
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case X86ISD::FMIN: return "X86ISD::FMIN";
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case X86ISD::FMIN: return "X86ISD::FMIN";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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@ -11053,6 +11058,36 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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}
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}
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static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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// Want to form PANDN nodes, in the hopes of then easily combining them with
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// OR and AND nodes to form PBLEND/PSIGN.
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EVT VT = N->getValueType(0);
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if (VT != MVT::v2i64)
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return SDValue();
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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DebugLoc DL = N->getDebugLoc();
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// Check LHS for vnot
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if (N0.getOpcode() == ISD::XOR &&
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ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
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return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
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// Check RHS for vnot
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if (N1.getOpcode() == ISD::XOR &&
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ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
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return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
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return SDValue();
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}
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static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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const X86Subtarget *Subtarget) {
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@ -11060,12 +11095,101 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
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if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
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return SDValue();
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return SDValue();
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// fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
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SDValue N0 = N->getOperand(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue N1 = N->getOperand(1);
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// look for psign/blend
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if (Subtarget->hasSSSE3()) {
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if (VT == MVT::v2i64) {
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// Canonicalize pandn to RHS
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if (N0.getOpcode() == X86ISD::PANDN)
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std::swap(N0, N1);
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// or (and (m, x), (pandn m, y))
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if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) {
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SDValue Mask = N1.getOperand(0);
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SDValue X = N1.getOperand(1);
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SDValue Y;
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if (N0.getOperand(0) == Mask)
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Y = N0.getOperand(1);
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if (N0.getOperand(1) == Mask)
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Y = N0.getOperand(0);
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// Check to see if the mask appeared in both the AND and PANDN and
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if (!Y.getNode())
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return SDValue();
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// Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
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if (Mask.getOpcode() != ISD::BITCAST ||
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X.getOpcode() != ISD::BITCAST ||
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Y.getOpcode() != ISD::BITCAST)
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return SDValue();
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// Look through mask bitcast.
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Mask = Mask.getOperand(0);
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EVT MaskVT = Mask.getValueType();
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// Validate that the Mask operand is a vector sra node. The sra node
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// will be an intrinsic.
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if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
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return SDValue();
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// FIXME: what to do for bytes, since there is a psignb/pblendvb, but
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// there is no psrai.b
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switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
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case Intrinsic::x86_sse2_psrai_w:
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case Intrinsic::x86_sse2_psrai_d:
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break;
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default: return SDValue();
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}
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// Check that the SRA is all signbits.
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SDValue SraC = Mask.getOperand(2);
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unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
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unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
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if ((SraAmt + 1) != EltBits)
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return SDValue();
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DebugLoc DL = N->getDebugLoc();
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// Now we know we at least have a plendvb with the mask val. See if
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// we can form a psignb/w/d.
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// psign = x.type == y.type == mask.type && y = sub(0, x);
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X = X.getOperand(0);
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Y = Y.getOperand(0);
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if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
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ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
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X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
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unsigned Opc = 0;
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switch (EltBits) {
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case 8: Opc = X86ISD::PSIGNB; break;
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case 16: Opc = X86ISD::PSIGNW; break;
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case 32: Opc = X86ISD::PSIGND; break;
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default: break;
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}
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if (Opc) {
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SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
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return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
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}
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}
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// PBLENDVB only available on SSE 4.1
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if (!Subtarget->hasSSE41())
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return SDValue();
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unsigned IID = Intrinsic::x86_sse41_pblendvb;
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X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
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Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
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Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
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Mask = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::v16i8,
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DAG.getConstant(IID, MVT::i32), X, Y, Mask);
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return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
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}
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}
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}
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// fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
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if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
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if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
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std::swap(N0, N1);
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std::swap(N0, N1);
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if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
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if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
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@ -11116,7 +11240,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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DAG.getNode(ISD::TRUNCATE, DL,
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DAG.getNode(ISD::TRUNCATE, DL,
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MVT::i8, ShAmt0));
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MVT::i8, ShAmt0));
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}
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}
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return SDValue();
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return SDValue();
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}
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}
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@ -11334,6 +11458,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::SHL:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRA:
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case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
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case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
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case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
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case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
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case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
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case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
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case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
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case X86ISD::FXOR:
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case X86ISD::FXOR:
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@ -159,7 +159,13 @@ namespace llvm {
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/// PSHUFB - Shuffle 16 8-bit values within a vector.
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/// PSHUFB - Shuffle 16 8-bit values within a vector.
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PSHUFB,
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PSHUFB,
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/// PANDN - and with not'd value.
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PANDN,
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/// PSIGNB/W/D - Copy integer sign.
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PSIGNB, PSIGNW, PSIGND,
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/// FMAX, FMIN - Floating point max and min.
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/// FMAX, FMIN - Floating point max and min.
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///
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///
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FMAX, FMIN,
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FMAX, FMIN,
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@ -43,6 +43,18 @@ def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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SDTCisSameAs<0,2>]>>;
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def X86pandn : SDNode<"X86ISD::PANDN",
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SDTypeProfile<1, 2, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignb : SDNode<"X86ISD::PSIGNB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignw : SDNode<"X86ISD::PSIGNW",
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SDTypeProfile<1, 2, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignd : SDNode<"X86ISD::PSIGND",
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SDTypeProfile<1, 2, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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@ -1584,19 +1584,13 @@ defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
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let isCommutable = 0 in
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let isCommutable = 0 in
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defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
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defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
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// single r+r
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// single r+r
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[(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
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[(set VR128:$dst, (X86pandn VR128:$src1, VR128:$src2))],
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(bc_v2i64 (v4i32 immAllOnesV))),
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VR128:$src2)))],
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// double r+r
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// double r+r
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[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
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[],
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(bc_v2i64 (v2f64 VR128:$src2))))],
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// single r+m
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// single r+m
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[(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
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[(set VR128:$dst, (X86pandn VR128:$src1, (memopv2i64 addr:$src2)))],
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(bc_v2i64 (v4i32 immAllOnesV))),
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(memopv2i64 addr:$src2))))],
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// double r+m
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// double r+m
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[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
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[]]>;
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(memopv2i64 addr:$src2)))]]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Arithmetic Instructions
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// SSE 1 & 2 - Arithmetic Instructions
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@ -2536,15 +2530,11 @@ let ExeDomain = SSEPackedInt in {
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}
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}
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def PANDNrr : PDI<0xDF, MRMSrcReg,
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def PANDNrr : PDI<0xDF, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"pandn\t{$src2, $dst|$dst, $src2}",
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"pandn\t{$src2, $dst|$dst, $src2}", []>;
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[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
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VR128:$src2)))]>;
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def PANDNrm : PDI<0xDF, MRMSrcMem,
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def PANDNrm : PDI<0xDF, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
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"pandn\t{$src2, $dst|$dst, $src2}",
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"pandn\t{$src2, $dst|$dst, $src2}", []>;
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[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
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(memopv2i64 addr:$src2))))]>;
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}
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}
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} // Constraints = "$src1 = $dst"
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} // Constraints = "$src1 = $dst"
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@ -3608,6 +3598,13 @@ def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
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(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
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def : Pat<(X86psignb VR128:$src1, VR128:$src2),
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(PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
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def : Pat<(X86psignw VR128:$src1, VR128:$src2),
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(PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
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def : Pat<(X86psignd VR128:$src1, VR128:$src2),
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(PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Align Instruction Patterns
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// SSSE3 - Packed Align Instruction Patterns
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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@ -3896,27 +3893,6 @@ def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
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def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
|
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
|
||||||
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
|
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
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||||||
|
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||||||
// Some special case pandn patterns.
|
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def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
|
||||||
VR128:$src2)),
|
|
||||||
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
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||||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
|
||||||
VR128:$src2)),
|
|
||||||
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
||||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
|
||||||
VR128:$src2)),
|
|
||||||
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
||||||
|
|
||||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
|
||||||
(memop addr:$src2))),
|
|
||||||
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
|
||||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
|
||||||
(memop addr:$src2))),
|
|
||||||
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
|
||||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
|
||||||
(memop addr:$src2))),
|
|
||||||
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
|
||||||
|
|
||||||
// vector -> vector casts
|
// vector -> vector casts
|
||||||
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
|
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
|
||||||
(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
|
(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
|
||||||
|
26
test/CodeGen/X86/vec-sign.ll
Normal file
26
test/CodeGen/X86/vec-sign.ll
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
; RUN: llc < %s -mcpu=nehalem | FileCheck %s
|
||||||
|
|
||||||
|
define <4 x i32> @psignd(<4 x i32> %a, <4 x i32> %b) nounwind ssp {
|
||||||
|
entry:
|
||||||
|
; CHECK: psignd
|
||||||
|
; CHECK-NOT: sub
|
||||||
|
%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
|
||||||
|
%sub = sub nsw <4 x i32> zeroinitializer, %a
|
||||||
|
%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||||
|
%1 = and <4 x i32> %a, %0
|
||||||
|
%2 = and <4 x i32> %b.lobit, %sub
|
||||||
|
%cond = or <4 x i32> %1, %2
|
||||||
|
ret <4 x i32> %cond
|
||||||
|
}
|
||||||
|
|
||||||
|
define <4 x i32> @pblendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind ssp {
|
||||||
|
entry:
|
||||||
|
; CHECK: pblendvb
|
||||||
|
%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
|
||||||
|
%sub = sub nsw <4 x i32> zeroinitializer, %a
|
||||||
|
%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
|
||||||
|
%1 = and <4 x i32> %c, %0
|
||||||
|
%2 = and <4 x i32> %a, %b.lobit
|
||||||
|
%cond = or <4 x i32> %1, %2
|
||||||
|
ret <4 x i32> %cond
|
||||||
|
}
|
Loading…
Reference in New Issue
Block a user