mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
Unify the patterns for loads and stores. Now offset addressing should be
supported. This almost completes memory operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
4e62951282
commit
b6718607c5
@ -40,9 +40,11 @@ class InstAlpha<bits<6> op, dag OL, string asmstr>
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}
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//3.3.1
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class MFormD<bits<6> opcode, string asmstr, list<dag> pattern>
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class MForm<bits<6> opcode, bit store, bit load, string asmstr, list<dag> pattern>
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: InstAlphaAlt<opcode, asmstr> {
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let Pattern = pattern;
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let isStore = store;
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let isLoad = load;
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bits<5> Ra;
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bits<16> disp;
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@ -62,16 +64,6 @@ class MFormAlt<bits<6> opcode, string asmstr>
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> {
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bits<5> Ra;
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@ -82,17 +74,6 @@ class MfcForm<bits<6> opcode, bits<16> fc, string asmstr>
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let Inst{15-0} = fc;
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}
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class MgForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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bits<5> Ra;
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bits<5> Rb;
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@ -439,125 +439,110 @@ def BR : BForm<0x30, "br $RA,$DISP">; //Branch
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def BR_DAG : BFormD<0x30, "br $$31,$DISP">; //Branch
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let OperandList = (ops GPRC:$RA, GPRC:$RB), disp = 0 in {
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let isLoad = 1 in {
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def LDQdag : MFormD<0x29, "ldq $RA,0($RB)",
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[(set GPRC:$RA, (load GPRC:$RB))]>;
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def LDLdag : MFormD<0x29, "ldl $RA,0($RB)",
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[(set GPRC:$RA, (sextload GPRC:$RB, i32))]>;
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def LDBUdag : MFormD<0x0A, "ldbu $RA,0($RB)",
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[(set GPRC:$RA, (zextload GPRC:$RB, i8))]>;
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def LDWUdag : MFormD<0x0C, "ldwu $RA,0($RB)",
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[(set GPRC:$RA, (zextload GPRC:$RB, i16))]>;
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}
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let isStore = 1 in {
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def STBdag : MFormD<0x0E, "stb $RA,0($RB)",
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[(truncstore GPRC:$RA, GPRC:$RB, i8)]>;
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def STWdag : MFormD<0x0D, "stw $RA,0($RB)",
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[(truncstore GPRC:$RA, GPRC:$RB, i16)]>;
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def STLdag : MFormD<0x2C, "stl $RA,0($RB)",
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[(truncstore GPRC:$RA, GPRC:$RB, i32)]>;
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def STQdag : MFormD<0x2D, "stq $RA,0($RB)",
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[(store GPRC:$RA, GPRC:$RB)]>;
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}
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}
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def : Pat<(i64 (extload GPRC:$src, i8)),
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(LDBUdag GPRC:$src)>;
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def : Pat<(i64 (extload GPRC:$src, i16)),
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(LDWUdag GPRC:$src)>;
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def : Pat<(i64 (extload GPRC:$src, i32)),
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(LDLdag GPRC:$src)>;
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let OperandList = (ops F4RC:$RA, GPRC:$RB), disp = 0 in {
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let isStore = 1 in
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def STSdag : MFormD<0x26, "sts $RA,0($RB)",
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[(store F4RC:$RA, GPRC:$RB)]>;
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let isLoad = 1 in
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def LDSdag : MFormD<0x22, "lds $RA,0($RB)",
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[(set F4RC:$RA, (load GPRC:$RB))]>;
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}
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let OperandList = (ops F8RC:$RA, GPRC:$RB), disp = 0 in {
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let isStore = 1 in
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def STTdag : MFormD<0x27, "stt $RA,0($RB)",
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[(store F8RC:$RA, GPRC:$RB)]>;
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let isLoad = 1 in
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def LDTdag : MFormD<0x23, "ldt $RA,0($RB)",
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[(set F8RC:$RA, (load GPRC:$RB))]>;
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}
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let isStore = 1 in {
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//Stores, int
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def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
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def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
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def STL : MForm<0x2C, "stl $RA,$DISP($RB)">; // Store longword
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def STQ : MForm<0x2D, "stq $RA,$DISP($RB)">; //Store quadword
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//Stores, float
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STS : MFormAlt<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STT : MFormAlt<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
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}
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let isLoad = 1 in {
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//Loads, int
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def LDL : MForm<0x28, "ldl $RA,$DISP($RB)">; // Load sign-extended longword
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def LDQ : MForm<0x29, "ldq $RA,$DISP($RB)">; //Load quadword
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def LDBU : MForm<0x0A, "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
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def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
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//Loads, float
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDS : MFormAlt<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDT : MFormAlt<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
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}
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
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[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
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def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
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def LDL : MForm<0x29, 0, 1, "ldl $RA,$DISP($RB)",
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[(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))]>;
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def LDLr : MForm<0x29, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32))]>;
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def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
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[(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))]>;
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def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8))]>;
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def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
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[(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))]>;
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def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16))]>;
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def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
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[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)]>;
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def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
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[(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8)]>;
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def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
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[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i16)]>;
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def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
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[(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16)]>;
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def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
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[(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i32)]>;
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def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
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[(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32)]>;
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def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
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[(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
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def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
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[(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
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//Load address
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def LDA : MForm<0x08, "lda $RA,$DISP($RB)">; //Load address
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def LDAH : MForm<0x09, "ldah $RA,$DISP($RB)">; //Load address high
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let isLoad = 1 in {
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//Loads, int, Rellocated Low form
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def LDLr : MForm<0x28, "ldl $RA,$DISP($RB)\t\t!gprellow">; // Load sign-extended longword
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def LDQr : MForm<0x29, "ldq $RA,$DISP($RB)\t\t!gprellow">; //Load quadword
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def LDBUr : MForm<0x0A, "ldbu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extended byte
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def LDWUr : MForm<0x0C, "ldwu $RA,$DISP($RB)\t\t!gprellow">; //Load zero-extended word
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//Loads, float, Rellocated Low form
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDSr : MFormAlt<0x22, "lds $RA,$DISP($RB)\t\t!gprellow">; //Load S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def LDTr : MFormAlt<0x23, "ldt $RA,$DISP($RB)\t\t!gprellow">; //Load T_floating
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def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
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[(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
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def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
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[(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>; //Load address
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def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
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[]>; //Load address high
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def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
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[(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))]>; //Load address high
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}
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//Load address, rellocated low and high form
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def LDAr : MForm<0x08, "lda $RA,$DISP($RB)\t\t!gprellow">; //Load address
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def LDAHr : MForm<0x09, "ldah $RA,$DISP($RB)\t\t!gprelhigh">; //Load address high
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let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
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[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
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def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
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[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
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def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
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[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
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def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
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[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
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}
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let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
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[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))]>;
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def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
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[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))]>;
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def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
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[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
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def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
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[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))]>;
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}
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//misc ext patterns
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def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
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(LDBU immSExt16:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i16)),
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(LDWU immSExt16:$DISP, GPRC:$RB)>;
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def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i32)),
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(LDL immSExt16:$DISP, GPRC:$RB)>;
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//0 disp patterns
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def : Pat<(i64 (load GPRC:$addr)),
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(LDQ 0, GPRC:$addr)>;
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def : Pat<(f64 (load GPRC:$addr)),
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(LDT 0, GPRC:$addr)>;
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def : Pat<(f32 (load GPRC:$addr)),
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(LDS 0, GPRC:$addr)>;
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def : Pat<(i64 (sextload GPRC:$addr, i32)),
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(LDL 0, GPRC:$addr)>;
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def : Pat<(i64 (zextload GPRC:$addr, i16)),
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(LDWU 0, GPRC:$addr)>;
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def : Pat<(i64 (zextload GPRC:$addr, i8)),
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(LDBU 0, GPRC:$addr)>;
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def : Pat<(i64 (extload GPRC:$addr, i8)),
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(LDBU 0, GPRC:$addr)>;
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def : Pat<(i64 (extload GPRC:$addr, i16)),
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(LDWU 0, GPRC:$addr)>;
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def : Pat<(i64 (extload GPRC:$addr, i32)),
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(LDL 0, GPRC:$addr)>;
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//load address, rellocated gpdist form
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def LDAg : MgForm<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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def LDAHg : MgForm<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
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def LDAg : MFormAlt<0x08, "lda $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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}
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//Load quad, rellocated literal form
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let isLoad = 1 in
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def LDQl : MForm<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
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let isStore = 1 in {
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//Stores, int
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def STBr : MForm<0x0E, "stb $RA,$DISP($RB)\t\t!gprellow">; // Store byte
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def STWr : MForm<0x0D, "stw $RA,$DISP($RB)\t\t!gprellow">; // Store word
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def STLr : MForm<0x2C, "stl $RA,$DISP($RB)\t\t!gprellow">; // Store longword
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def STQr : MForm<0x2D, "stq $RA,$DISP($RB)\t\t!gprellow">; //Store quadword
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//Stores, float
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let OperandList = (ops F4RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STSr : MFormAlt<0x26, "sts $RA,$DISP($RB)\t\t!gprellow">; //Store S_floating
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let OperandList = (ops F8RC:$RA, s16imm:$DISP, GPRC:$RB) in
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def STTr : MFormAlt<0x27, "stt $RA,$DISP($RB)\t\t!gprellow">; //Store T_floating
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}
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let isLoad = 1, OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
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def LDQl : MFormAlt<0x29, "ldq $RA,$DISP($RB)\t\t!literal">; //Load quadword
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//Branches, int
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def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
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@ -819,42 +804,3 @@ def : Pat<(fneg F4RC:$RB),
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def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
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(SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA),
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(CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;
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def : Pat<(Alpha_gprello tglobaladdr:$in, GPRC:$reg),
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(LDAr tglobaladdr:$in, GPRC:$reg)>;
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def : Pat<(Alpha_gprelhi tglobaladdr:$in, GPRC:$reg),
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(LDAHr tglobaladdr:$in, GPRC:$reg)>;
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//GOT Relative loads
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def : Pat<(i64 (load (Alpha_gprello tglobaladdr:$in, GPRC:$reg))),
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(LDQr tglobaladdr:$in, GPRC:$reg)>;
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def : Pat<(f64 (load (Alpha_gprello tglobaladdr:$in, GPRC:$reg))),
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(LDTr tglobaladdr:$in, GPRC:$reg)>;
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def : Pat<(f32 (load (Alpha_gprello tglobaladdr:$in, GPRC:$reg))),
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(LDSr tglobaladdr:$in, GPRC:$reg)>;
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def : Pat<(i64 (sextload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i32)),
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(LDLr tglobaladdr:$in, GPRC:$reg)>;
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def : Pat<(i64 (extload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i32)),
|
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(LDLr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (zextload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i16)),
|
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(LDWUr tglobaladdr:$in, GPRC:$reg)>;
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||||
def : Pat<(i64 (extload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i16)),
|
||||
(LDWUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (zextload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i8)),
|
||||
(LDBUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(i64 (extload (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i8)),
|
||||
(LDBUr tglobaladdr:$in, GPRC:$reg)>;
|
||||
|
||||
//GOT Relative Stores
|
||||
def : Pat<(store GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg)),
|
||||
(STQr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(store F8RC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg)),
|
||||
(STTr F8RC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(store F4RC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg)),
|
||||
(STSr F4RC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(truncstore GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i32),
|
||||
(STLr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(truncstore GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i16),
|
||||
(STWr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
def : Pat<(truncstore GPRC:$val, (Alpha_gprello tglobaladdr:$in, GPRC:$reg), i8),
|
||||
(STBr GPRC:$val, tglobaladdr:$in, GPRC:$reg)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user