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Fix PR1016

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31950 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-11-28 01:03:30 +00:00
parent 480f093dc2
commit b6c806045b
1 changed files with 4 additions and 5 deletions
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9
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -1862,6 +1862,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break;
case Promote:
Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
// Make sure the condition is either zero or one.
if (!TLI.MaskedValueIsZero(Tmp1,
MVT::getIntVTBitMask(Tmp1.getValueType())^1))
Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
break;
}
Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
@ -1883,11 +1887,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Tmp2, Tmp3,
cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
} else {
// Make sure the condition is either zero or one. It may have been
// promoted from something else.
unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
Result = DAG.getSelectCC(Tmp1,
DAG.getConstant(0, Tmp1.getValueType()),
Tmp2, Tmp3, ISD::SETNE);