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Added checking code whehter target supports specific dag combining about rotate

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or not. The corresponding dag patterns are as following:

"DAGCombier::MatchRotate" function in DAGCombiner.cpp
Pattern1
// fold (or (shl (*ext x), (*ext y)),
//          (srl (*ext x), (*ext (sub 32, y)))) ->
//   (*ext (rotl x, y))
// fold (or (shl (*ext x), (*ext y)),
//          (srl (*ext x), (*ext (sub 32, y)))) ->
//   (*ext (rotr x, (sub 32, y)))

pattern2
// fold (or (shl (*ext x), (*ext (sub 32, y))),
//          (srl (*ext x), (*ext y))) ->
//   (*ext (rotl x, y))
// fold (or (shl (*ext x), (*ext (sub 32, y))),
//          (srl (*ext x), (*ext y))) ->
//   (*ext (rotr x, (sub 32, y)))


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191905 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jin-Gu Kang 2013-10-03 15:58:48 +00:00
parent 4d63c8daec
commit b70a05a871
1 changed files with 19 additions and 11 deletions
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30
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3415,12 +3415,16 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
// (*ext (rotr x, (sub 32, y)))
SDValue LArgExtOp0 = LHSShiftArg.getOperand(0);
EVT LArgVT = LArgExtOp0.getValueType();
if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
SDValue V =
DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
}
bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT);
bool HasROTLWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTL, LArgVT);
if (HasROTRWithLArg || HasROTLWithLArg) {
if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
SDValue V =
DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
}
}
}
}
} else if (LExtOp0.getOpcode() == ISD::SUB &&
@ -3444,11 +3448,15 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
// (*ext (rotr x, (sub 32, y)))
SDValue RArgExtOp0 = RHSShiftArg.getOperand(0);
EVT RArgVT = RArgExtOp0.getValueType();
if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
SDValue V =
DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, RArgVT,
RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt);
return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode();
bool HasROTRWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTR, RArgVT);
bool HasROTLWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTL, RArgVT);
if (HasROTRWithRArg || HasROTLWithRArg) {
if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
SDValue V =
DAG.getNode(HasROTRWithRArg ? ISD::ROTR : ISD::ROTL, DL, RArgVT,
RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt);
return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode();
}
}
}
}