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lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
care of this ourselves git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21110 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,8 +42,8 @@ def IA64 : Target {
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//'special' GRs:
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r1, // global data pointer (GP)
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r12, // memory stack pointer (SP)
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// r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves
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// r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
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// **** r13 (thread pointer) we do not touch, ever. it's not here. ****//
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//r15, // our frame pointer (FP)
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