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Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -736,7 +736,7 @@ def postidx_reg : Operand<i32> {
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let DecoderMethod = "DecodePostIdxReg";
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let DecoderMethod = "DecodePostIdxReg";
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let PrintMethod = "printPostIdxRegOperand";
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let PrintMethod = "printPostIdxRegOperand";
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let ParserMatchClass = PostIdxRegAsmOperand;
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let ParserMatchClass = PostIdxRegAsmOperand;
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let MIOperandInfo = (ops GPR, i32imm);
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let MIOperandInfo = (ops GPRnopc, i32imm);
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}
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}
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@ -2484,7 +2484,7 @@ multiclass AI3ldrT<bits<4> op, string opc> {
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let Inst{3-0} = offset{3-0};
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let Inst{3-0} = offset{3-0};
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let AsmMatchConverter = "cvtLdExtTWriteBackImm";
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let AsmMatchConverter = "cvtLdExtTWriteBackImm";
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}
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}
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def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
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def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
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(ins addr_offset_none:$addr, postidx_reg:$Rm),
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(ins addr_offset_none:$addr, postidx_reg:$Rm),
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IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
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IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
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"\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
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"\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
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@ -2492,8 +2492,10 @@ multiclass AI3ldrT<bits<4> op, string opc> {
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let Inst{23} = Rm{4};
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let Inst{23} = Rm{4};
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let Inst{22} = 0;
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let Inst{22} = 0;
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let Inst{11-8} = 0;
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let Inst{11-8} = 0;
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let Unpredictable{11-8} = 0b1111;
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let Inst{3-0} = Rm{3-0};
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let Inst{3-0} = Rm{3-0};
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let AsmMatchConverter = "cvtLdExtTWriteBackReg";
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let AsmMatchConverter = "cvtLdExtTWriteBackReg";
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let DecoderMethod = "DecodeLDR";
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}
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}
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}
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}
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@ -323,8 +323,8 @@ static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeLDR(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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#include "ARMGenDisassemblerTables.inc"
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#include "ARMGenDisassemblerTables.inc"
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#include "ARMGenInstrInfo.inc"
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#include "ARMGenInstrInfo.inc"
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#include "ARMGenEDInfo.inc"
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#include "ARMGenEDInfo.inc"
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@ -3178,7 +3178,7 @@ static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
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unsigned add = fieldFromInstruction32(Insn, 4, 1);
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unsigned add = fieldFromInstruction32(Insn, 4, 1);
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if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
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if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
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return MCDisassembler::Fail;
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(add));
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Inst.addOperand(MCOperand::CreateImm(add));
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@ -4263,3 +4263,31 @@ static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
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return S;
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return S;
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}
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}
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static DecodeStatus DecodeLDR(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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unsigned Rn = fieldFromInstruction32(Val, 16, 4);
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unsigned Rt = fieldFromInstruction32(Val, 12, 4);
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unsigned Rm = fieldFromInstruction32(Val, 0, 4);
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Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
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unsigned Cond = fieldFromInstruction32(Val, 28, 4);
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if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
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S = MCDisassembler::SoftFail;
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if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
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return MCDisassembler::Fail;
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if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
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return MCDisassembler::Fail;
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return S;
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}
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22
test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt
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22
test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt
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@ -0,0 +1,22 @@
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# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
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# CHECK: potentially undefined
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# CHECK: 0xff 0x00 0xb9 0x00
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0xff 0x00 0xb9 0x00
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# CHECK: potentially undefined
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# CHECK: 0xfb 0xf0 0xb9 0x00
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0xfb 0xf0 0xb9 0x00
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# CHECK: potentially undefined
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# CHECK: 0xfb 0x01 0xb9 0x00
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0xfb 0x01 0xb9 0x00
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# CHECK: potentially undefined
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# CHECK: 0xfb 0x00 0xbf 0x00
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0xfb 0x00 0xbf 0x00
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# CHECK: potentially undefined
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# CHECK: 0xfb 0x90 0xb9 0x00
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0xfb 0x90 0xb9 0x00
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