mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Change Neon VLDn intrinsics to return multiple values instead of really
wide vectors. Likewise, change VSTn intrinsics to take separate arguments for each vector in a multi-vector struct. Adjust tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
09b1366f3f
commit
b7d0c90c44
@ -291,20 +291,56 @@ def int_arm_neon_vmovlu : Neon_1Arg_Long_Intrinsic;
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let TargetPrefix = "arm" in {
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// De-interleaving vector loads from N-element structures.
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def int_arm_neon_vldi : Intrinsic<[llvm_anyint_ty],
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[llvm_ptr_ty, llvm_i32_ty],
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[IntrReadArgMem]>;
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def int_arm_neon_vldf : Intrinsic<[llvm_anyfloat_ty],
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[llvm_ptr_ty, llvm_i32_ty],
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[IntrReadArgMem]>;
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def int_arm_neon_vld1i : Intrinsic<[llvm_anyint_ty],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld1f : Intrinsic<[llvm_anyfloat_ty],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld2i : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld2f : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld3i : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>,
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LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld3f : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>,
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LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld4i : Intrinsic<[llvm_anyint_ty, LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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def int_arm_neon_vld4f : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[llvm_ptr_ty], [IntrReadArgMem]>;
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// Interleaving vector stores from N-element structures.
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def int_arm_neon_vsti : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyint_ty, llvm_i32_ty],
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[IntrWriteArgMem]>;
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def int_arm_neon_vstf : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyfloat_ty,llvm_i32_ty],
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[IntrWriteArgMem]>;
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def int_arm_neon_vst1i : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyint_ty],
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[IntrWriteArgMem]>;
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def int_arm_neon_vst1f : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyfloat_ty],
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[IntrWriteArgMem]>;
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def int_arm_neon_vst2i : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyint_ty,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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def int_arm_neon_vst2f : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyfloat_ty,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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def int_arm_neon_vst3i : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyint_ty,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrWriteArgMem]>;
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def int_arm_neon_vst3f : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyfloat_ty,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrWriteArgMem]>;
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def int_arm_neon_vst4i : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyint_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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def int_arm_neon_vst4f : Intrinsic<[llvm_void_ty],
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[llvm_ptr_ty, llvm_anyfloat_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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// Vector Table Lookup
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def int_arm_neon_vtbl : Intrinsic<[llvm_v8i8_ty],
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@ -135,45 +135,45 @@ def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
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class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
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!strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
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[(set DPR:$dst, (Ty (IntOp addrmode6:$addr, 1)))]>;
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[(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
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class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
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!strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
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[(set QPR:$dst, (Ty (IntOp addrmode6:$addr, 1)))]>;
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[(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
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def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vldi>;
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def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vldi>;
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def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vldi>;
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def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vldf>;
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def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vldi>;
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def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
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def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
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def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
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def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
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def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
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def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vldi>;
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def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vldi>;
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def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vldi>;
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def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vldf>;
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def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vldi>;
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def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
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def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
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def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
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def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
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def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
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// VST1 : Vector Store (multiple single elements)
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class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
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!strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
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[(IntOp addrmode6:$addr, (Ty DPR:$src), 1)]>;
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[(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
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class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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: NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
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!strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
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[(IntOp addrmode6:$addr, (Ty QPR:$src), 1)]>;
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[(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
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def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vsti>;
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def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vsti>;
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def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vsti>;
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def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vstf>;
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def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vsti>;
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def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
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def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
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def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
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def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
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def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
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def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vsti>;
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def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vsti>;
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def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vsti>;
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def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vstf>;
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def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vsti>;
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def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
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def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
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def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
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def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
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def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
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//===----------------------------------------------------------------------===//
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@ -5,63 +5,63 @@
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; RUN: grep {vld1\\.64} %t | count 2
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define <8 x i8> @vld1i8(i8* %A) nounwind {
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%tmp1 = call <8 x i8> @llvm.arm.neon.vldi.v8i8(i8* %A, i32 1)
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%tmp1 = call <8 x i8> @llvm.arm.neon.vld1i.v8i8(i8* %A)
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ret <8 x i8> %tmp1
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}
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define <4 x i16> @vld1i16(i16* %A) nounwind {
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%tmp1 = call <4 x i16> @llvm.arm.neon.vldi.v4i16(i16* %A, i32 1)
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%tmp1 = call <4 x i16> @llvm.arm.neon.vld1i.v4i16(i16* %A)
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ret <4 x i16> %tmp1
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}
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define <2 x i32> @vld1i32(i32* %A) nounwind {
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%tmp1 = call <2 x i32> @llvm.arm.neon.vldi.v2i32(i32* %A, i32 1)
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%tmp1 = call <2 x i32> @llvm.arm.neon.vld1i.v2i32(i32* %A)
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ret <2 x i32> %tmp1
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}
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define <2 x float> @vld1f(float* %A) nounwind {
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%tmp1 = call <2 x float> @llvm.arm.neon.vldf.v2f32(float* %A, i32 1)
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%tmp1 = call <2 x float> @llvm.arm.neon.vld1f.v2f32(float* %A)
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ret <2 x float> %tmp1
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}
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define <1 x i64> @vld1i64(i64* %A) nounwind {
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%tmp1 = call <1 x i64> @llvm.arm.neon.vldi.v1i64(i64* %A, i32 1)
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%tmp1 = call <1 x i64> @llvm.arm.neon.vld1i.v1i64(i64* %A)
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ret <1 x i64> %tmp1
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}
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define <16 x i8> @vld1Qi8(i8* %A) nounwind {
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%tmp1 = call <16 x i8> @llvm.arm.neon.vldi.v16i8(i8* %A, i32 1)
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%tmp1 = call <16 x i8> @llvm.arm.neon.vld1i.v16i8(i8* %A)
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ret <16 x i8> %tmp1
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}
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define <8 x i16> @vld1Qi16(i16* %A) nounwind {
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%tmp1 = call <8 x i16> @llvm.arm.neon.vldi.v8i16(i16* %A, i32 1)
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%tmp1 = call <8 x i16> @llvm.arm.neon.vld1i.v8i16(i16* %A)
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ret <8 x i16> %tmp1
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}
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define <4 x i32> @vld1Qi32(i32* %A) nounwind {
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%tmp1 = call <4 x i32> @llvm.arm.neon.vldi.v4i32(i32* %A, i32 1)
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%tmp1 = call <4 x i32> @llvm.arm.neon.vld1i.v4i32(i32* %A)
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ret <4 x i32> %tmp1
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}
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define <4 x float> @vld1Qf(float* %A) nounwind {
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%tmp1 = call <4 x float> @llvm.arm.neon.vldf.v4f32(float* %A, i32 1)
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%tmp1 = call <4 x float> @llvm.arm.neon.vld1f.v4f32(float* %A)
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ret <4 x float> %tmp1
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}
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define <2 x i64> @vld1Qi64(i64* %A) nounwind {
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%tmp1 = call <2 x i64> @llvm.arm.neon.vldi.v2i64(i64* %A, i32 1)
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%tmp1 = call <2 x i64> @llvm.arm.neon.vld1i.v2i64(i64* %A)
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ret <2 x i64> %tmp1
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}
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declare <8 x i8> @llvm.arm.neon.vldi.v8i8(i8*, i32) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vldi.v4i16(i16*, i32) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vldi.v2i32(i32*, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vldf.v2f32(float*, i32) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vldi.v1i64(i64*, i32) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vld1i.v8i8(i8*) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vld1i.v4i16(i16*) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vld1i.v2i32(i32*) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vld1f.v2f32(float*) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vld1i.v1i64(i64*) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vldi.v16i8(i8*, i32) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vldi.v8i16(i16*, i32) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vldi.v4i32(i32*, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vldf.v4f32(float*, i32) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vldi.v2i64(i64*, i32) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vld1i.v16i8(i8*) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vld1i.v8i16(i16*) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vld1i.v4i32(i32*) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vld1f.v4f32(float*) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vld1i.v2i64(i64*) nounwind readnone
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@ -6,72 +6,72 @@
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define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vsti.v8i8(i8* %A, <8 x i8> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1i.v8i8(i8* %A, <8 x i8> %tmp1)
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ret void
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}
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define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vsti.v4i16(i16* %A, <4 x i16> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1i.v4i16(i16* %A, <4 x i16> %tmp1)
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ret void
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}
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define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vsti.v2i32(i32* %A, <2 x i32> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1i.v2i32(i32* %A, <2 x i32> %tmp1)
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ret void
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}
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define void @vst1f(float* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vstf.v2f32(float* %A, <2 x float> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1f.v2f32(float* %A, <2 x float> %tmp1)
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ret void
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}
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define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
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%tmp1 = load <1 x i64>* %B
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call void @llvm.arm.neon.vsti.v1i64(i64* %A, <1 x i64> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1i.v1i64(i64* %A, <1 x i64> %tmp1)
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ret void
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}
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define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %B
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call void @llvm.arm.neon.vsti.v16i8(i8* %A, <16 x i8> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1i.v16i8(i8* %A, <16 x i8> %tmp1)
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ret void
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}
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define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vsti.v8i16(i16* %A, <8 x i16> %tmp1, i32 1)
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call void @llvm.arm.neon.vst1i.v8i16(i16* %A, <8 x i16> %tmp1)
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ret void
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}
|
||||
|
||||
define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
|
||||
%tmp1 = load <4 x i32>* %B
|
||||
call void @llvm.arm.neon.vsti.v4i32(i32* %A, <4 x i32> %tmp1, i32 1)
|
||||
call void @llvm.arm.neon.vst1i.v4i32(i32* %A, <4 x i32> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
|
||||
%tmp1 = load <4 x float>* %B
|
||||
call void @llvm.arm.neon.vstf.v4f32(float* %A, <4 x float> %tmp1, i32 1)
|
||||
call void @llvm.arm.neon.vst1f.v4f32(float* %A, <4 x float> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
|
||||
%tmp1 = load <2 x i64>* %B
|
||||
call void @llvm.arm.neon.vsti.v2i64(i64* %A, <2 x i64> %tmp1, i32 1)
|
||||
call void @llvm.arm.neon.vst1i.v2i64(i64* %A, <2 x i64> %tmp1)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.arm.neon.vsti.v8i8(i8*, <8 x i8>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vsti.v4i16(i16*, <4 x i16>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vsti.v2i32(i32*, <2 x i32>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vstf.v2f32(float*, <2 x float>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vsti.v1i64(i64*, <1 x i64>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v8i8(i8*, <8 x i8>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v4i16(i16*, <4 x i16>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v2i32(i32*, <2 x i32>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1f.v2f32(float*, <2 x float>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v1i64(i64*, <1 x i64>) nounwind readnone
|
||||
|
||||
declare void @llvm.arm.neon.vsti.v16i8(i8*, <16 x i8>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vsti.v8i16(i16*, <8 x i16>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vsti.v4i32(i32*, <4 x i32>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vstf.v4f32(float*, <4 x float>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vsti.v2i64(i64*, <2 x i64>, i32) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v16i8(i8*, <16 x i8>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v8i16(i16*, <8 x i16>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v4i32(i32*, <4 x i32>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1f.v4f32(float*, <4 x float>) nounwind readnone
|
||||
declare void @llvm.arm.neon.vst1i.v2i64(i64*, <2 x i64>) nounwind readnone
|
||||
|
||||
Loading…
Reference in New Issue
Block a user