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Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christopher Lamb 2007-08-10 21:18:25 +00:00
parent 8b165731bc
commit b81337117c
2 changed files with 70 additions and 10 deletions
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57
lib/Target/X86/X86InstrInfo.cpp
View File

@ -19,6 +19,7 @@
#include "X86TargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/SSARegMap.h"
using namespace llvm;
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
@ -209,17 +210,53 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
}
case X86::SHL16ri: {
assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
if (DisableLEA16) return 0;
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
// NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
// the flags produced by a shift yet, so this is safe.
unsigned Dest = MI->getOperand(0).getReg();
unsigned Src = MI->getOperand(1).getReg();
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 0 || ShAmt >= 4) return 0;
NewMI = BuildMI(get(X86::LEA16r), Dest)
.addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
if (DisableLEA16) {
// If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
unsigned Opc, leaInReg, leaOutReg;
MVT::ValueType leaVT;
if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
Opc = X86::LEA64_32r;
leaVT = MVT::i64;
leaInReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
leaOutReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
} else {
Opc = X86::LEA32r;
leaVT = MVT::i32;
leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
}
MachineInstr *Ins = NULL, *Ext = NULL;
Ins = BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
Ins->copyKillDeadInfo(MI);
NewMI = BuildMI(get(Opc), leaOutReg)
.addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
Ext = BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
Ext->copyKillDeadInfo(MI);
MFI->insert(MBBI, Ins); // Insert the insert_subreg
LV.instructionChanged(MI, NewMI); // Update live variables
LV.addVirtualRegisterKilled(leaInReg, NewMI);
MFI->insert(MBBI, NewMI); // Insert the new inst
LV.addVirtualRegisterKilled(leaOutReg, Ext);
MFI->insert(MBBI, Ext); // Insert the extract_subreg
return Ext;
} else {
NewMI = BuildMI(get(X86::LEA16r), Dest)
.addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
}
break;
}
}

23
test/CodeGen/X86/2007-08-10-LEA16Use32.ll Normal file
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@ -0,0 +1,23 @@
; RUN: llvm-as < %s | llc -march=x86 | grep {leal}
@X = global i16 0 ; <i16*> [#uses=1]
@Y = global i16 0 ; <i16*> [#uses=1]
define void @_Z3fooi(i32 %N) {
entry:
%tmp1019 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
br i1 %tmp1019, label %bb, label %return
bb: ; preds = %bb, %entry
%i.014.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
%tmp1 = trunc i32 %i.014.0 to i16 ; <i16> [#uses=2]
volatile store i16 %tmp1, i16* @X, align 2
%tmp34 = shl i16 %tmp1, 2 ; <i16> [#uses=1]
volatile store i16 %tmp34, i16* @Y, align 2
%indvar.next = add i32 %i.014.0, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry
ret void
}