6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-01 03:33:42 +00:00
Code Issues Projects Releases Wiki Activity

Mips assembler: Explicit floating point condition register recognition.

Browse Source 
This patch allows the assembler to recognize $fcc0 
as a valid register for conditional move instructions. 

Corresponding test cases have been added.

Contributer: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter 2013-04-15 22:21:55 +00:00
parent 3fe91a4453
commit b8145e3881
2 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -778,6 +778,9 @@ int MipsAsmParser::matchCPURegisterName(StringRef Name) {
}
int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
if (Name.equals("fcc0"))
return Mips::FCC0;
int CC;
CC = matchCPURegisterName(Name);
if (CC != -1)

4
test/MC/Mips/mips-fpu-instructions.s
View File

@ -156,6 +156,8 @@
# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48]
# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
# CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
# CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00]
cfc1 $a2,$0
mfc1 $a2,$f7
@ -175,3 +177,5 @@
mtc0 $9, $8, 3
mfc2 $5, $7, 4
mtc2 $9, $4, 5
movf $2, $1, $fcc0
movt $2, $1, $fcc0