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Mips assembler: Explicit floating point condition register recognition.
This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -778,6 +778,9 @@ int MipsAsmParser::matchCPURegisterName(StringRef Name) {
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}
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int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
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if (Name.equals("fcc0"))
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return Mips::FCC0;
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int CC;
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CC = matchCPURegisterName(Name);
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if (CC != -1)
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@ -156,6 +156,8 @@
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# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
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# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48]
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# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
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# CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
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# CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00]
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cfc1 $a2,$0
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mfc1 $a2,$f7
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@ -175,3 +177,5 @@
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mtc0 $9, $8, 3
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mfc2 $5, $7, 4
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mtc2 $9, $4, 5
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movf $2, $1, $fcc0
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movt $2, $1, $fcc0
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