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Added register reassignment prototype to RAGreedy. It's a simple

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heuristic to reshuffle register assignments when we can't find an
available reg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2010-12-09 18:15:21 +00:00
parent f2f516fc26
commit b853e6c370
5 changed files with 116 additions and 19 deletions
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5
lib/CodeGen/LiveIntervalUnion.cpp
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@ -247,10 +247,13 @@ collectInterferingVRegs(unsigned MaxInterferingRegs) {
if (!IR.LiveUnionI.value()->isSpillable())
SeenUnspillableVReg = true;
InterferingVRegs.push_back(IR.LiveUnionI.value());
if (InterferingVRegs.size() == MaxInterferingRegs)
// Leave SeenAllInterferences set to false to indicate that at least one
// interference exists beyond those we collected.
return MaxInterferingRegs;
InterferingVRegs.push_back(IR.LiveUnionI.value());
// Cache the most recent interfering vreg to bypass isSeenInterference.
RecentInterferingVReg = IR.LiveUnionI.value();
++IR.LiveUnionI;