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Added register reassignment prototype to RAGreedy. It's a simple

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heuristic to reshuffle register assignments when we can't find an
available reg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2010-12-09 18:15:21 +00:00
parent f2f516fc26
commit b853e6c370
5 changed files with 116 additions and 19 deletions
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4
lib/CodeGen/RegAllocBasic.cpp
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@ -435,15 +435,13 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
LiveInterval *interferingVirtReg =
Queries[interfReg].firstInterference().liveUnionPos().value();
// The current VirtReg must either spillable, or one of its interferences
// The current VirtReg must either be spillable, or one of its interferences
// must have less spill weight.
if (interferingVirtReg->weight < VirtReg.weight ) {
PhysRegSpillCands.push_back(PhysReg);
}
}
// Try to spill another interfering reg with less spill weight.
//
// FIXME: RAGreedy will sort this list by spill weight.
for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {