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Fix command-line option printing to print two spaces where needed,

Browse Source 
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-10-14 20:25:08 +00:00
parent b34dd13a0f
commit b8cab9227a
26 changed files with 43 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/RegAllocBigBlock.cpp
View File

@ -53,7 +53,7 @@ STATISTIC(NumLoads , "Number of loads added");
STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
static RegisterRegAlloc
bigBlockRegAlloc("bigblock", " Big-block register allocator",
bigBlockRegAlloc("bigblock", "Big-block register allocator",
createBigBlockRegisterAllocator);
namespace {

2
lib/CodeGen/RegAllocLinearScan.cpp
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@ -50,7 +50,7 @@ NewHeuristic("new-spilling-heuristic",
cl::init(false), cl::Hidden);
static RegisterRegAlloc
linearscanRegAlloc("linearscan", " linear scan register allocator",
linearscanRegAlloc("linearscan", "linear scan register allocator",
createLinearScanRegisterAllocator);
namespace {

2
lib/CodeGen/RegAllocLocal.cpp
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@ -37,7 +37,7 @@ STATISTIC(NumStores, "Number of stores added");
STATISTIC(NumLoads , "Number of loads added");
static RegisterRegAlloc
localRegAlloc("local", " local register allocator",
localRegAlloc("local", "local register allocator",
createLocalRegisterAllocator);
namespace {

2
lib/CodeGen/RegAllocPBQP.cpp
View File

@ -60,7 +60,7 @@
using namespace llvm;
static RegisterRegAlloc
registerPBQPRepAlloc("pbqp", " PBQP register allocator",
registerPBQPRepAlloc("pbqp", "PBQP register allocator",
createPBQPRegisterAllocator);

2
lib/CodeGen/RegAllocSimple.cpp
View File

@ -35,7 +35,7 @@ STATISTIC(NumLoads , "Number of loads added");
namespace {
static RegisterRegAlloc
simpleRegAlloc("simple", " simple register allocator",
simpleRegAlloc("simple", "simple register allocator",
createSimpleRegisterAllocator);
class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {

2
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -31,7 +31,7 @@ STATISTIC(NumDups, "Number of duplicated nodes");
STATISTIC(NumCCCopies, "Number of cross class copies");
static RegisterScheduler
fastDAGScheduler("fast", " Fast suboptimal list scheduling",
fastDAGScheduler("fast", "Fast suboptimal list scheduling",
createFastDAGScheduler);
namespace {

2
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
View File

@ -37,7 +37,7 @@ STATISTIC(NumNoops , "Number of noops inserted");
STATISTIC(NumStalls, "Number of pipeline stalls");
static RegisterScheduler
tdListDAGScheduler("list-td", " Top-down list scheduler",
tdListDAGScheduler("list-td", "Top-down list scheduler",
createTDListDAGScheduler);
namespace {

4
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -41,11 +41,11 @@ STATISTIC(NumCCCopies, "Number of cross class copies");
static RegisterScheduler
burrListDAGScheduler("list-burr",
" Bottom-up register reduction list scheduling",
"Bottom-up register reduction list scheduling",
createBURRListDAGScheduler);
static RegisterScheduler
tdrListrDAGScheduler("list-tdrr",
" Top-down register reduction list scheduling",
"Top-down register reduction list scheduling",
createTDRRListDAGScheduler);
namespace {

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -119,7 +119,7 @@ ISHeuristic("pre-RA-sched",
" allocation):"));
static RegisterScheduler
defaultListDAGScheduler("default", " Best scheduler for the target",
defaultListDAGScheduler("default", "Best scheduler for the target",
createDefaultScheduler);
namespace llvm {

4
lib/CodeGen/VirtRegMap.cpp
View File

@ -56,8 +56,8 @@ static cl::opt<SpillerName>
SpillerOpt("spiller",
cl::desc("Spiller to use: (default: local)"),
cl::Prefix,
cl::values(clEnumVal(simple, " simple spiller"),
clEnumVal(local, " local spiller"),
cl::values(clEnumVal(simple, "simple spiller"),
clEnumVal(local, "local spiller"),
clEnumValEnd),
cl::init(local));

2
lib/Support/CommandLine.cpp
View File

@ -953,7 +953,7 @@ void generic_parser_base::printOptionInfo(const Option &O,
for (unsigned i = 0, e = getNumOptions(); i != e; ++i) {
size_t NumSpaces = GlobalWidth-strlen(getOption(i))-8;
cout << " =" << getOption(i) << std::string(NumSpaces, ' ')
<< " - " << getDescription(i) << "\n";
<< " - " << getDescription(i) << "\n";
}
} else {
if (O.HelpStr[0])

4
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -29,8 +29,8 @@ static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
cl::desc("Disable if-conversion pass"));
// Register the target.
static RegisterTarget<ARMTargetMachine> X("arm", " ARM");
static RegisterTarget<ThumbTargetMachine> Y("thumb", " Thumb");
static RegisterTarget<ARMTargetMachine> X("arm", "ARM");
static RegisterTarget<ThumbTargetMachine> Y("thumb", "Thumb");
// No assembler printer by default
ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0;

2
lib/Target/Alpha/AlphaTargetMachine.cpp
View File

@ -22,7 +22,7 @@
using namespace llvm;
// Register the targets
static RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
static RegisterTarget<AlphaTargetMachine> X("alpha", "Alpha (incomplete)");
const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
return new AlphaTargetAsmInfo(*this);

2
lib/Target/CBackend/CBackend.cpp
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@ -49,7 +49,7 @@
using namespace llvm;
// Register the target.
static RegisterTarget<CTargetMachine> X("c", " C backend");
static RegisterTarget<CTargetMachine> X("c", "C backend");
namespace {
/// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for

2
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -24,7 +24,7 @@ using namespace llvm;
namespace {
// Register the targets
RegisterTarget<SPUTargetMachine>
CELLSPU("cellspu", " STI CBEA Cell SPU");
CELLSPU("cellspu", "STI CBEA Cell SPU");
}
const std::pair<unsigned, int> *

2
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -72,7 +72,7 @@ static cl::opt<std::string> NameToGenerate("cppfor", cl::Optional,
cl::init("!bad!"));
// Register the target.
static RegisterTarget<CPPTargetMachine> X("cpp", " C++ backend");
static RegisterTarget<CPPTargetMachine> X("cpp", "C++ backend");
namespace {
typedef std::vector<const Type*> TypeList;

2
lib/Target/IA64/IA64TargetMachine.cpp
View File

@ -26,7 +26,7 @@ using namespace llvm;
extern "C" int IA64TargetMachineModule;
int IA64TargetMachineModule = 0;
static RegisterTarget<IA64TargetMachine> X("ia64", " IA-64 (Itanium)");
static RegisterTarget<IA64TargetMachine> X("ia64", "IA-64 (Itanium)");
const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const {
return new IA64TargetAsmInfo(*this);

2
lib/Target/MSIL/MSILWriter.cpp
View File

@ -45,7 +45,7 @@ namespace {
}
static RegisterTarget<MSILTarget> X("msil", " MSIL backend");
static RegisterTarget<MSILTarget> X("msil", "MSIL backend");
bool MSILModule::runOnModule(Module &M) {
ModulePtr = &M;

4
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -20,8 +20,8 @@
using namespace llvm;
// Register the target.
static RegisterTarget<MipsTargetMachine> X("mips", " Mips");
static RegisterTarget<MipselTargetMachine> Y("mipsel", " Mipsel");
static RegisterTarget<MipsTargetMachine> X("mips", "Mips");
static RegisterTarget<MipselTargetMachine> Y("mipsel", "Mipsel");
const TargetAsmInfo *MipsTargetMachine::
createTargetAsmInfo() const

2
lib/Target/PIC16/PIC16TargetMachine.cpp
View File

@ -23,7 +23,7 @@ using namespace llvm;
namespace {
// Register the targets
RegisterTarget<PIC16TargetMachine> X("pic16", " PIC16 14-bit");
RegisterTarget<PIC16TargetMachine> X("pic16", "PIC16 14-bit");
}
PIC16TargetMachine::

4
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -23,9 +23,9 @@ using namespace llvm;
// Register the targets
static RegisterTarget<PPC32TargetMachine>
X("ppc32", " PowerPC 32");
X("ppc32", "PowerPC 32");
static RegisterTarget<PPC64TargetMachine>
Y("ppc64", " PowerPC 64");
Y("ppc64", "PowerPC 64");
// No assembler printer by default
PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;

2
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -19,7 +19,7 @@
using namespace llvm;
// Register the target.
static RegisterTarget<SparcTargetMachine> X("sparc", " SPARC");
static RegisterTarget<SparcTargetMachine> X("sparc", "SPARC");
const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
// FIXME: Handle Solaris subtarget someday :)

18
lib/Target/TargetMachine.cpp
View File

@ -102,13 +102,13 @@ DefRelocationModel(
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
" Target default relocation model"),
"Target default relocation model"),
clEnumValN(Reloc::Static, "static",
" Non-relocatable code"),
"Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
" Fully relocatable, position independent code"),
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
" Relocatable external references, non-relocatable code"),
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
static cl::opt<llvm::CodeModel::Model, true>
DefCodeModel(
@ -118,15 +118,15 @@ DefCodeModel(
cl::init(CodeModel::Default),
cl::values(
clEnumValN(CodeModel::Default, "default",
" Target default code model"),
"Target default code model"),
clEnumValN(CodeModel::Small, "small",
" Small code model"),
"Small code model"),
clEnumValN(CodeModel::Kernel, "kernel",
" Kernel code model"),
"Kernel code model"),
clEnumValN(CodeModel::Medium, "medium",
" Medium code model"),
"Medium code model"),
clEnumValN(CodeModel::Large, "large",
" Large code model"),
"Large code model"),
clEnumValEnd));
static cl::opt<bool, true>

4
lib/Target/X86/X86Subtarget.cpp
View File

@ -23,8 +23,8 @@ static cl::opt<X86Subtarget::AsmWriterFlavorTy>
AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
cl::desc("Choose style of code to emit from X86 backend:"),
cl::values(
clEnumValN(X86Subtarget::ATT, "att", " Emit AT&T-style assembly"),
clEnumValN(X86Subtarget::Intel, "intel", " Emit Intel-style assembly"),
clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
clEnumValEnd));

4
lib/Target/X86/X86TargetMachine.cpp
View File

@ -32,9 +32,9 @@ int X86TargetMachineModule = 0;
// Register the target.
static RegisterTarget<X86_32TargetMachine>
X("x86", " 32-bit X86: Pentium-Pro and above");
X("x86", "32-bit X86: Pentium-Pro and above");
static RegisterTarget<X86_64TargetMachine>
Y("x86-64", " 64-bit X86: EM64T and AMD64");
Y("x86-64", "64-bit X86: EM64T and AMD64");
// No assembler printer by default
X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0;

6
tools/llc/llc.cpp
View File

@ -80,11 +80,11 @@ FileType("filetype", cl::init(TargetMachine::AssemblyFile),
cl::desc("Choose a file type (not all types are supported by all targets):"),
cl::values(
clEnumValN(TargetMachine::AssemblyFile, "asm",
" Emit an assembly ('.s') file"),
"Emit an assembly ('.s') file"),
clEnumValN(TargetMachine::ObjectFile, "obj",
" Emit a native object ('.o') file [experimental]"),
"Emit a native object ('.o') file [experimental]"),
clEnumValN(TargetMachine::DynamicLibrary, "dynlib",
" Emit a native dynamic library ('.so') file"
"Emit a native dynamic library ('.so') file"
" [experimental]"),
clEnumValEnd));