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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -53,7 +53,7 @@ STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumFolded, "Number of loads/stores folded into instructions");
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static RegisterRegAlloc
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bigBlockRegAlloc("bigblock", " Big-block register allocator",
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bigBlockRegAlloc("bigblock", "Big-block register allocator",
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createBigBlockRegisterAllocator);
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namespace {
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@ -50,7 +50,7 @@ NewHeuristic("new-spilling-heuristic",
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cl::init(false), cl::Hidden);
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static RegisterRegAlloc
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linearscanRegAlloc("linearscan", " linear scan register allocator",
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linearscanRegAlloc("linearscan", "linear scan register allocator",
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createLinearScanRegisterAllocator);
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namespace {
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@ -37,7 +37,7 @@ STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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static RegisterRegAlloc
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localRegAlloc("local", " local register allocator",
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localRegAlloc("local", "local register allocator",
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createLocalRegisterAllocator);
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namespace {
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@ -60,7 +60,7 @@
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using namespace llvm;
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static RegisterRegAlloc
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registerPBQPRepAlloc("pbqp", " PBQP register allocator",
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registerPBQPRepAlloc("pbqp", "PBQP register allocator",
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createPBQPRegisterAllocator);
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@ -35,7 +35,7 @@ STATISTIC(NumLoads , "Number of loads added");
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namespace {
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static RegisterRegAlloc
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simpleRegAlloc("simple", " simple register allocator",
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simpleRegAlloc("simple", "simple register allocator",
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createSimpleRegisterAllocator);
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class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
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@ -31,7 +31,7 @@ STATISTIC(NumDups, "Number of duplicated nodes");
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STATISTIC(NumCCCopies, "Number of cross class copies");
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static RegisterScheduler
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fastDAGScheduler("fast", " Fast suboptimal list scheduling",
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fastDAGScheduler("fast", "Fast suboptimal list scheduling",
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createFastDAGScheduler);
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namespace {
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@ -37,7 +37,7 @@ STATISTIC(NumNoops , "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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static RegisterScheduler
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tdListDAGScheduler("list-td", " Top-down list scheduler",
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tdListDAGScheduler("list-td", "Top-down list scheduler",
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createTDListDAGScheduler);
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namespace {
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@ -41,11 +41,11 @@ STATISTIC(NumCCCopies, "Number of cross class copies");
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static RegisterScheduler
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burrListDAGScheduler("list-burr",
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" Bottom-up register reduction list scheduling",
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"Bottom-up register reduction list scheduling",
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createBURRListDAGScheduler);
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static RegisterScheduler
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tdrListrDAGScheduler("list-tdrr",
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" Top-down register reduction list scheduling",
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"Top-down register reduction list scheduling",
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createTDRRListDAGScheduler);
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namespace {
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@ -119,7 +119,7 @@ ISHeuristic("pre-RA-sched",
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" allocation):"));
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static RegisterScheduler
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defaultListDAGScheduler("default", " Best scheduler for the target",
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defaultListDAGScheduler("default", "Best scheduler for the target",
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createDefaultScheduler);
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namespace llvm {
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@ -56,8 +56,8 @@ static cl::opt<SpillerName>
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SpillerOpt("spiller",
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cl::desc("Spiller to use: (default: local)"),
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cl::Prefix,
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cl::values(clEnumVal(simple, " simple spiller"),
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clEnumVal(local, " local spiller"),
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cl::values(clEnumVal(simple, "simple spiller"),
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clEnumVal(local, "local spiller"),
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clEnumValEnd),
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cl::init(local));
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@ -953,7 +953,7 @@ void generic_parser_base::printOptionInfo(const Option &O,
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for (unsigned i = 0, e = getNumOptions(); i != e; ++i) {
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size_t NumSpaces = GlobalWidth-strlen(getOption(i))-8;
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cout << " =" << getOption(i) << std::string(NumSpaces, ' ')
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<< " - " << getDescription(i) << "\n";
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<< " - " << getDescription(i) << "\n";
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}
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} else {
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if (O.HelpStr[0])
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@ -29,8 +29,8 @@ static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
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cl::desc("Disable if-conversion pass"));
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// Register the target.
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static RegisterTarget<ARMTargetMachine> X("arm", " ARM");
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static RegisterTarget<ThumbTargetMachine> Y("thumb", " Thumb");
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static RegisterTarget<ARMTargetMachine> X("arm", "ARM");
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static RegisterTarget<ThumbTargetMachine> Y("thumb", "Thumb");
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// No assembler printer by default
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ARMTargetMachine::AsmPrinterCtorFn ARMTargetMachine::AsmPrinterCtor = 0;
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@ -22,7 +22,7 @@
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using namespace llvm;
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// Register the targets
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static RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
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static RegisterTarget<AlphaTargetMachine> X("alpha", "Alpha (incomplete)");
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const TargetAsmInfo *AlphaTargetMachine::createTargetAsmInfo() const {
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return new AlphaTargetAsmInfo(*this);
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@ -49,7 +49,7 @@
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using namespace llvm;
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// Register the target.
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static RegisterTarget<CTargetMachine> X("c", " C backend");
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static RegisterTarget<CTargetMachine> X("c", "C backend");
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namespace {
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/// CBackendNameAllUsedStructsAndMergeFunctions - This pass inserts names for
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@ -24,7 +24,7 @@ using namespace llvm;
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namespace {
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// Register the targets
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RegisterTarget<SPUTargetMachine>
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CELLSPU("cellspu", " STI CBEA Cell SPU");
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CELLSPU("cellspu", "STI CBEA Cell SPU");
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}
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const std::pair<unsigned, int> *
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@ -72,7 +72,7 @@ static cl::opt<std::string> NameToGenerate("cppfor", cl::Optional,
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cl::init("!bad!"));
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// Register the target.
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static RegisterTarget<CPPTargetMachine> X("cpp", " C++ backend");
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static RegisterTarget<CPPTargetMachine> X("cpp", "C++ backend");
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namespace {
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typedef std::vector<const Type*> TypeList;
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@ -26,7 +26,7 @@ using namespace llvm;
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extern "C" int IA64TargetMachineModule;
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int IA64TargetMachineModule = 0;
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static RegisterTarget<IA64TargetMachine> X("ia64", " IA-64 (Itanium)");
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static RegisterTarget<IA64TargetMachine> X("ia64", "IA-64 (Itanium)");
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const TargetAsmInfo *IA64TargetMachine::createTargetAsmInfo() const {
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return new IA64TargetAsmInfo(*this);
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@ -45,7 +45,7 @@ namespace {
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}
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static RegisterTarget<MSILTarget> X("msil", " MSIL backend");
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static RegisterTarget<MSILTarget> X("msil", "MSIL backend");
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bool MSILModule::runOnModule(Module &M) {
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ModulePtr = &M;
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@ -20,8 +20,8 @@
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using namespace llvm;
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// Register the target.
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static RegisterTarget<MipsTargetMachine> X("mips", " Mips");
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static RegisterTarget<MipselTargetMachine> Y("mipsel", " Mipsel");
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static RegisterTarget<MipsTargetMachine> X("mips", "Mips");
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static RegisterTarget<MipselTargetMachine> Y("mipsel", "Mipsel");
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const TargetAsmInfo *MipsTargetMachine::
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createTargetAsmInfo() const
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@ -23,7 +23,7 @@ using namespace llvm;
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namespace {
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// Register the targets
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RegisterTarget<PIC16TargetMachine> X("pic16", " PIC16 14-bit");
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RegisterTarget<PIC16TargetMachine> X("pic16", "PIC16 14-bit");
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}
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PIC16TargetMachine::
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@ -23,9 +23,9 @@ using namespace llvm;
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// Register the targets
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static RegisterTarget<PPC32TargetMachine>
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X("ppc32", " PowerPC 32");
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X("ppc32", "PowerPC 32");
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static RegisterTarget<PPC64TargetMachine>
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Y("ppc64", " PowerPC 64");
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Y("ppc64", "PowerPC 64");
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// No assembler printer by default
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PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
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using namespace llvm;
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// Register the target.
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static RegisterTarget<SparcTargetMachine> X("sparc", " SPARC");
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static RegisterTarget<SparcTargetMachine> X("sparc", "SPARC");
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const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
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// FIXME: Handle Solaris subtarget someday :)
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@ -102,13 +102,13 @@ DefRelocationModel(
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cl::init(Reloc::Default),
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cl::values(
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clEnumValN(Reloc::Default, "default",
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" Target default relocation model"),
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"Target default relocation model"),
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clEnumValN(Reloc::Static, "static",
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" Non-relocatable code"),
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"Non-relocatable code"),
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clEnumValN(Reloc::PIC_, "pic",
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" Fully relocatable, position independent code"),
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"Fully relocatable, position independent code"),
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clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
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" Relocatable external references, non-relocatable code"),
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"Relocatable external references, non-relocatable code"),
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clEnumValEnd));
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static cl::opt<llvm::CodeModel::Model, true>
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DefCodeModel(
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@ -118,15 +118,15 @@ DefCodeModel(
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cl::init(CodeModel::Default),
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cl::values(
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clEnumValN(CodeModel::Default, "default",
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" Target default code model"),
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"Target default code model"),
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clEnumValN(CodeModel::Small, "small",
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" Small code model"),
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"Small code model"),
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clEnumValN(CodeModel::Kernel, "kernel",
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" Kernel code model"),
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"Kernel code model"),
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clEnumValN(CodeModel::Medium, "medium",
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" Medium code model"),
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"Medium code model"),
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clEnumValN(CodeModel::Large, "large",
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" Large code model"),
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"Large code model"),
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clEnumValEnd));
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static cl::opt<bool, true>
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AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
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cl::desc("Choose style of code to emit from X86 backend:"),
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cl::values(
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clEnumValN(X86Subtarget::ATT, "att", " Emit AT&T-style assembly"),
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clEnumValN(X86Subtarget::Intel, "intel", " Emit Intel-style assembly"),
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clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
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clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
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clEnumValEnd));
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// Register the target.
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static RegisterTarget<X86_32TargetMachine>
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X("x86", " 32-bit X86: Pentium-Pro and above");
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X("x86", "32-bit X86: Pentium-Pro and above");
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static RegisterTarget<X86_64TargetMachine>
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Y("x86-64", " 64-bit X86: EM64T and AMD64");
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Y("x86-64", "64-bit X86: EM64T and AMD64");
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// No assembler printer by default
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X86TargetMachine::AsmPrinterCtorFn X86TargetMachine::AsmPrinterCtor = 0;
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cl::desc("Choose a file type (not all types are supported by all targets):"),
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cl::values(
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clEnumValN(TargetMachine::AssemblyFile, "asm",
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" Emit an assembly ('.s') file"),
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"Emit an assembly ('.s') file"),
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clEnumValN(TargetMachine::ObjectFile, "obj",
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" Emit a native object ('.o') file [experimental]"),
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"Emit a native object ('.o') file [experimental]"),
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clEnumValN(TargetMachine::DynamicLibrary, "dynlib",
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" Emit a native dynamic library ('.so') file"
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"Emit a native dynamic library ('.so') file"
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" [experimental]"),
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clEnumValEnd));
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