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https://github.com/c64scene-ar/llvm-6502.git
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Match TargetInstrInfo changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32098 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -433,8 +433,7 @@ static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
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for (unsigned j = i+1; j < e; ++j) {
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MachineOperand &MO2 = MI->getOperand(j);
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if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
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TII->getOperandConstraint(MI->getOpcode(), j,
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TargetInstrInfo::TIED_TO) == (int)i)
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TII->getOperandConstraint(MI->getOpcode(),j,TOI::TIED_TO) == (int)i)
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return true;
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}
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}
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@ -127,8 +127,7 @@ void ScheduleDAG::BuildSchedUnits() {
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if (MainNode->isTargetOpcode()) {
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unsigned Opc = MainNode->getTargetOpcode();
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for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
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if (TII->getOperandConstraint(Opc, i,
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TargetInstrInfo::TIED_TO) != -1) {
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if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
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SU->isTwoAddress = true;
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break;
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}
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@ -128,8 +128,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
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unsigned NumRes = CountResults(SU->Node);
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unsigned NumOps = CountOperands(SU->Node);
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for (unsigned j = 0; j != NumOps; ++j) {
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if (TII->getOperandConstraint(Opc, j+NumRes,
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TargetInstrInfo::TIED_TO) == -1)
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if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
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continue;
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SDNode *OpN = SU->Node->getOperand(j).Val;
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@ -498,8 +497,7 @@ namespace {
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unsigned NumRes = ScheduleDAG::CountResults(SU1->Node);
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unsigned NumOps = ScheduleDAG::CountOperands(SU1->Node);
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for (unsigned i = 0; i != NumOps; ++i) {
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if (TII->getOperandConstraint(Opc, i+NumRes,
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TargetInstrInfo::TIED_TO) == -1)
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if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) == -1)
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continue;
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if (SU1->Node->getOperand(i).isOperand(SU2->Node))
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return true;
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@ -667,8 +665,7 @@ bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
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unsigned NumRes = ScheduleDAG::CountResults(SU->Node);
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unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
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for (unsigned i = 0; i != NumOps; ++i) {
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if (TII->getOperandConstraint(Opc, i+NumRes,
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TargetInstrInfo::TIED_TO) != -1) {
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if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
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SDNode *DU = SU->Node->getOperand(i).Val;
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if (Op == (*SUnitMap)[DU])
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return true;
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@ -698,8 +695,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
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unsigned NumRes = ScheduleDAG::CountResults(Node);
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unsigned NumOps = ScheduleDAG::CountOperands(Node);
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for (unsigned j = 0; j != NumOps; ++j) {
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if (TII->getOperandConstraint(Opc, j+NumRes,
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TargetInstrInfo::TIED_TO) != -1) {
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if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
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SDNode *DU = SU->Node->getOperand(j).Val;
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SUnit *DUSU = (*SUnitMap)[DU];
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if (!DUSU) continue;
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@ -79,8 +79,8 @@ void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DOUT << "Machine Function\n";
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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LiveVariables &LV = getAnalysis<LiveVariables>();
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bool MadeChange = false;
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@ -92,11 +92,11 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
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mi != me; ++mi) {
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unsigned opcode = mi->getOpcode();
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const TargetInstrDescriptor *TID = mi->getInstrDescriptor();
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bool FirstTied = true;
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for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) {
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int ti = TII.getOperandConstraint(opcode, si, TargetInstrInfo::TIED_TO);
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for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
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int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
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if (ti == -1)
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continue;
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@ -139,13 +139,11 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!LV.KillsRegister(mi, regB)) {
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const TargetInstrDescriptor &TID = TII.get(opcode);
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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if ((TID.Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
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if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
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assert(mi->getOperand(3-si).isRegister() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(3-si).getReg();
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@ -173,20 +171,17 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
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if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR)
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// FIXME: This assumes there are no more operands which are tied
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// to another register.
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#ifndef NDEBUG
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for (unsigned i = si+1, e = TII.getNumOperands(opcode); i < e; ++i)
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assert(TII.getOperandConstraint(opcode, i,
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TargetInstrInfo::TIED_TO) == -1);
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for (unsigned i = si+1, e = TID->numOperands; i < e; ++i)
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assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
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#endif
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if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
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if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
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DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
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DOUT << "2addr: TO 3-ADDR: " << *New;
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LV.instructionChanged(mi, New); // Update live variables
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mbbi->insert(mi, New); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = New;
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++NumConvertedTo3Addr;
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@ -97,8 +97,7 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
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}
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ModRef MRInfo;
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if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo,
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TargetInstrInfo::TIED_TO)) {
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if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo, TOI::TIED_TO)) {
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// Folded a two-address operand.
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MRInfo = isModRef;
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} else if (OldMI->getOperand(OpNo).isDef()) {
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@ -592,8 +591,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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// aren't allowed to modify the reused register. If none of these cases
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// apply, reuse it.
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bool CanReuse = true;
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int ti = TII->getOperandConstraint(MI.getOpcode(), i,
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TargetInstrInfo::TIED_TO);
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int ti = TII->getOperandConstraint(MI.getOpcode(), i, TOI::TIED_TO);
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if (ti != -1 &&
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MI.getOperand(ti).isReg() &&
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MI.getOperand(ti).getReg() == VirtReg) {
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@ -32,7 +32,7 @@ TargetInstrInfo::findTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
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for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) {
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if (i == OpNum)
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continue;
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int ti = getOperandConstraint(Opc, i, TIED_TO);
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int ti = getOperandConstraint(Opc, i, TOI::TIED_TO);
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if (ti == (int)OpNum)
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return i;
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}
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@ -471,7 +471,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
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unsigned NumOps = II->getNumOperands(Opcode);
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if (NumOps) {
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bool isTwoAddr = NumOps > 1 &&
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II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1;
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II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1;
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// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
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bool isTrunc8 = isX86_64TruncToByte(Opcode);
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@ -610,7 +610,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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unsigned NumOps = II->getNumOperands(Opcode);
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unsigned CurOp = 0;
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if (NumOps > 1 &&
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II->getOperandConstraint(Opcode, 1, TargetInstrInfo::TIED_TO) != -1)
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II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1)
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CurOp++;
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unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
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@ -252,7 +252,9 @@ public:
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const;
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables &LV) const;
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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@ -289,7 +289,7 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
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bool isTwoAddrFold = false;
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unsigned NumOps = TII.getNumOperands(MI->getOpcode());
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bool isTwoAddr = NumOps > 1 &&
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TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1;
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TII.getOperandConstraint(MI->getOpcode(), 1, TOI::TIED_TO) != -1;
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MachineInstr *NewMI = NULL;
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// Folding a memory location into the two-address part of a two-address
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