6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-28 06:58:19 +00:00
Code Issues Projects Releases Wiki Activity

* Make a PPC32-specific code emitter because we have separate classes for 32-

Browse Source 
and 64-bit code emitters that cannot share code unless we use virtual
  functions
* Identify components being built by tablegen with more detail by assigning them
  to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building
  PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16980 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-10-14 06:04:56 +00:00
parent a645750722
commit bab2adf496
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/PowerPC/Makefile
View File

@ -14,14 +14,14 @@ TARGET = PowerPC
# Make sure that tblgen is run, first thing.
$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
PowerPCGenCodeEmitter.inc PowerPCGenAsmWriter.inc \
PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
@echo "Building PowerPC register names with tblgen"
@echo "Building $(TARGET) register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
@ -37,14 +37,14 @@ $(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET) instruction information with tblgen"
@echo "Building `basename $<` instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
$(TARGET)GenCodeEmitter.inc:: PPC32.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET) code emitter"
%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
@echo "Building `basename $<` code emitter with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
$(TARGET)GenAsmWriter.inc:: PowerPC.td $(TDFILES) $(TBLGEN)
$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td assembly writer with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@