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Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mihai Popa 2013-05-20 14:42:43 +00:00
parent 44b486ed78
commit bac932e9c3
2 changed files with 3 additions and 3 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1048,7 +1048,7 @@ static const uint16_t QPRDecoderTable[] = {
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
if (RegNo > 31)
if (RegNo > 31 || (RegNo & 1) != 0)
return MCDisassembler::Fail;
RegNo >>= 1;

4
test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
View File

@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding"
# XFAIL: *
# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
@ -9,3 +8,4 @@
#
# Qm -> bit[0] == 0, otherwise UNDEFINED
0xdb 0xe0 0x40 0xf2
# CHECK: invalid instruction encoding