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More APInt-ification.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47868 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2008-03-03 23:35:36 +00:00
parent 3370dd70ae
commit bb271ff9fe
1 changed files with 6 additions and 10 deletions
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16
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@@ -1518,17 +1518,13 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
return VTBits-Tmp; return VTBits-Tmp;
case ISD::Constant: { case ISD::Constant: {
uint64_t Val = cast<ConstantSDNode>(Op)->getValue(); const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
// If negative, invert the bits, then look at it. // If negative, return # leading ones.
if (Val & MVT::getIntVTSignBit(VT)) if (Val.isNegative())
Val = ~Val; return Val.countLeadingOnes();
// Shift the bits so they are the leading bits in the int64_t. // Return # leading zeros.
Val <<= 64-VTBits; return Val.countLeadingZeros();
// Return # leading zeros. We use 'min' here in case Val was zero before
// shifting. We don't want to return '64' as for an i32 "0".
return std::min(VTBits, CountLeadingZeros_64(Val));
} }
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND: