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RegScavenger interface change to make it more flexible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34690 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -27,16 +27,34 @@ class TargetRegisterClass;
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class RegScavenger {
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MachineBasicBlock *MBB;
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MachineBasicBlock::iterator MBBI;
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bool MBBIInited;
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unsigned NumPhysRegs;
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/// Initialized - All states are initialized and ready to go!
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bool Initialized;
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/// RegStates - The current state of all the physical registers immediately
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/// before MBBI. One bit per physical register. If bit is set that means it's
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/// available, unset means the register is currently being used.
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BitVector RegStates;
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public:
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RegScavenger(MachineBasicBlock *mbb);
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RegScavenger()
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: MBB(NULL), Initialized(false) {};
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RegScavenger(MachineBasicBlock *mbb)
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: MBB(mbb), Initialized(false) {};
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/// Init - Initialize the states.
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///
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void init();
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/// Reset - Discard previous states and re-initialize the states given for
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/// the specific basic block.
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void reset(MachineBasicBlock *mbb) {
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MBB = mbb;
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clear();
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init();
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}
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/// forward / backward - Move the internal MBB iterator and update register
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/// states.
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@ -45,8 +63,12 @@ public:
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/// forward / backward - Move the internal MBB iterator and update register
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/// states until it has reached but not processed the specific iterator.
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void forward(MachineBasicBlock::iterator I);
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void backward(MachineBasicBlock::iterator I);
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void forward(MachineBasicBlock::iterator I) {
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while (MBBI != I) forward();
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}
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void backward(MachineBasicBlock::iterator I) {
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while (MBBI != I) backward();
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}
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/// isReserved - Returns true if a register is reserved. It is never "unused".
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bool isReserved(unsigned Reg) const { return ReservedRegs[Reg]; }
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@ -69,10 +91,16 @@ public:
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bool ExCalleeSaved = false) const;
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private:
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/// clear - Clear states.
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///
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void clear();
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/// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
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///
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BitVector CalleeSavedRegs;
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/// ReservedRegs - A bitvector of reserved registers.
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///
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BitVector ReservedRegs;
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};
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@ -25,12 +25,12 @@
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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RegScavenger::RegScavenger(MachineBasicBlock *mbb)
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: MBB(mbb), MBBIInited(false) {
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void RegScavenger::init() {
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const MachineFunction &MF = *MBB->getParent();
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RegInfo = TM.getRegisterInfo();
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MBBI = MBB->begin();
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NumPhysRegs = RegInfo->getNumRegs();
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RegStates.resize(NumPhysRegs, true);
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@ -50,15 +50,16 @@ RegScavenger::RegScavenger(MachineBasicBlock *mbb)
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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setUsed(*I);
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Initialized = true;
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}
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void RegScavenger::forward() {
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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// Move ptr forward.
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if (!MBBIInited) {
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MBBI = MBB->begin();
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MBBIInited = true;
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} else
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if (!Initialized)
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init();
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else
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MBBI = next(MBBI);
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MachineInstr *MI = MBBI;
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@ -133,16 +134,6 @@ void RegScavenger::backward() {
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setUsed(ChangedRegs);
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}
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void RegScavenger::forward(MachineBasicBlock::iterator I) {
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while (MBBI != I)
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forward();
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}
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void RegScavenger::backward(MachineBasicBlock::iterator I) {
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while (MBBI != I)
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backward();
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}
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/// CreateRegClassMask - Set the bits that represent the registers in the
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/// TargetRegisterClass.
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static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
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@ -167,3 +158,14 @@ unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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int Reg = RegStatesCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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}
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void RegScavenger::clear() {
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if (MBB) {
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MBBI = MBB->end();
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MBB = NULL;
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}
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NumPhysRegs = 0;
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Initialized = false;
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RegStates.clear();
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}
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