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Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196192 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5122,6 +5122,27 @@ defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
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USQADDbb, USQADDhh,
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USQADDss, USQADDdd>;
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def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
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(v1i64 FPR64:$Rn))),
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(SUQADDdd FPR64:$Src, FPR64:$Rn)>;
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def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
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(v1i64 FPR64:$Rn))),
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(USQADDdd FPR64:$Src, FPR64:$Rn)>;
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def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
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(ABSdd FPR64:$Rn)>;
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def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
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(SQABSdd FPR64:$Rn)>;
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def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
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(SQNEGdd FPR64:$Rn)>;
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def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
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(v1i64 FPR64:$Rn))),
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(NEGdd FPR64:$Rn)>;
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// Scalar Signed Saturating Extract Unsigned Narrow
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defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
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defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
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60
test/CodeGen/AArch64/neon-misc-scalar.ll
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60
test/CodeGen/AArch64/neon-misc-scalar.ll
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@ -0,0 +1,60 @@
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;RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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declare <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64>)
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declare <1 x i64> @llvm.arm.neon.vqabs.v1i64(<1 x i64>)
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declare <1 x i64> @llvm.arm.neon.vabs.v1i64(<1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>)
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define <1 x i64> @test_vuqadd_s64(<1 x i64> %a, <1 x i64> %b) {
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entry:
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; CHECK: test_vuqadd_s64
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%vuqadd2.i = tail call <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64> %a, <1 x i64> %b)
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; CHECK: suqadd d{{[0-9]+}}, d{{[0-9]+}}
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ret <1 x i64> %vuqadd2.i
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}
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define <1 x i64> @test_vsqadd_u64(<1 x i64> %a, <1 x i64> %b) {
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entry:
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; CHECK: test_vsqadd_u64
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%vsqadd2.i = tail call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %a, <1 x i64> %b)
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; CHECK: usqadd d{{[0-9]+}}, d{{[0-9]+}}
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ret <1 x i64> %vsqadd2.i
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}
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define <1 x i64> @test_vabs_s64(<1 x i64> %a) {
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; CHECK: test_vabs_s64
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entry:
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%vabs1.i = tail call <1 x i64> @llvm.arm.neon.vabs.v1i64(<1 x i64> %a)
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; CHECK: abs d{{[0-9]+}}, d{{[0-9]+}}
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ret <1 x i64> %vabs1.i
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}
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define <1 x i64> @test_vqabs_s64(<1 x i64> %a) {
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; CHECK: test_vqabs_s64
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entry:
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%vqabs1.i = tail call <1 x i64> @llvm.arm.neon.vqabs.v1i64(<1 x i64> %a)
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; CHECK: sqabs d{{[0-9]+}}, d{{[0-9]+}}
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ret <1 x i64> %vqabs1.i
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}
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define <1 x i64> @test_vqneg_s64(<1 x i64> %a) {
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; CHECK: test_vqneg_s64
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entry:
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%vqneg1.i = tail call <1 x i64> @llvm.arm.neon.vqneg.v1i64(<1 x i64> %a)
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; CHECK: sqneg d{{[0-9]+}}, d{{[0-9]+}}
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ret <1 x i64> %vqneg1.i
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}
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define <1 x i64> @test_vneg_s64(<1 x i64> %a) {
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; CHECK: test_vneg_s64
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entry:
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%sub.i = sub <1 x i64> zeroinitializer, %a
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; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
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ret <1 x i64> %sub.i
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}
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