6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-13 23:29:56 +00:00
Code Issues Projects Releases Wiki Activity

Filter out patterns that have PredicateOperands.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109572 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-07-28 01:52:23 +00:00
parent 81f9121cda
commit bc16827be6
1 changed files with 12 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
utils/TableGen/FastISelEmitter.cpp
View File

@ -54,6 +54,7 @@ struct OperandsSignature {
bool initialize(TreePatternNode *InstPatNode,
const CodeGenTarget &Target,
MVT::SimpleValueType VT) {
if (!InstPatNode->isLeaf()) {
if (InstPatNode->getOperator()->getName() == "imm") {
Operands.push_back("i");
@ -69,6 +70,7 @@ struct OperandsSignature {
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
// For now, filter out any operand with a predicate.
// For now, filter out any operand with multiple values.
if (!Op->getPredicateFns().empty() ||
@ -105,6 +107,7 @@ struct OperandsSignature {
RC = Target.getRegisterClassForRegister(OpLeafRec);
else
return false;
// For now, require the register operands' register classes to all
// be the same.
if (!RC)
@ -262,6 +265,15 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) {
if (II.OperandList.empty())
continue;
// For now ignore instructions that have predicate operands.
bool HasPredicate = false;
for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) {
if(II.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
HasPredicate = true;
}
if (HasPredicate)
continue;
// For now, ignore multi-instruction patterns.
bool MultiInsts = false;
for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {