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Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some verification when we're expanding variants. I had to refine the verification a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1032,11 +1032,13 @@ static bool hasVariant(ArrayRef<PredTransition> Transitions,
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// Populate IntersectingVariants with any variants or aliased sequences of the
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// given SchedRW whose processor indices and predicates are not mutually
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// exclusive with the given transition,
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// exclusive with the given transition.
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void PredTransitions::getIntersectingVariants(
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const CodeGenSchedRW &SchedRW, unsigned TransIdx,
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std::vector<TransVariant> &IntersectingVariants) {
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bool GenericRW = false;
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std::vector<TransVariant> Variants;
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if (SchedRW.HasVariants) {
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unsigned VarProcIdx = 0;
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@ -1048,6 +1050,8 @@ void PredTransitions::getIntersectingVariants(
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const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
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for (RecIter RI = VarDefs.begin(), RE = VarDefs.end(); RI != RE; ++RI)
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Variants.push_back(TransVariant(*RI, SchedRW.Index, VarProcIdx, 0));
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if (VarProcIdx == 0)
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GenericRW = true;
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}
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for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
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AI != AE; ++AI) {
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@ -1071,6 +1075,8 @@ void PredTransitions::getIntersectingVariants(
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Variants.push_back(
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TransVariant(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0));
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}
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if (AliasProcIdx == 0)
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GenericRW = true;
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}
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for (unsigned VIdx = 0, VEnd = Variants.size(); VIdx != VEnd; ++VIdx) {
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TransVariant &Variant = Variants[VIdx];
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@ -1108,6 +1114,10 @@ void PredTransitions::getIntersectingVariants(
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TransVec.push_back(TransVec[TransIdx]);
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}
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}
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if (GenericRW && IntersectingVariants.empty()) {
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PrintFatalError(SchedRW.TheDef->getLoc(), "No variant of this type has "
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"a matching predicate on any processor");
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}
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}
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// Push the Reads/Writes selected by this variant onto the PredTransition
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@ -1205,10 +1215,6 @@ void PredTransitions::substituteVariantOperand(
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// This will push a copies of TransVec[TransIdx] on the back of TransVec.
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std::vector<TransVariant> IntersectingVariants;
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getIntersectingVariants(SchedRW, TransIdx, IntersectingVariants);
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if (IntersectingVariants.empty())
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PrintFatalError(SchedRW.TheDef->getLoc(),
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"No variant of this type has "
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"a matching predicate on any processor");
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// Now expand each variant on top of its copy of the transition.
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for (std::vector<TransVariant>::const_iterator
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IVI = IntersectingVariants.begin(),
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