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Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:
_test: lis r2, 743 li r3, 0 stw r3, 32751(r2) blr instead of: _test: li r2, 0 stw r2, 32751(48693248) blr Implement support for ppc64 as well, allowing it to produce better code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34371 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -743,14 +743,18 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
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Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
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return true;
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}
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// FIXME: Handle small sext constant offsets in PPC64 mode also!
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if (CN->getValueType(0) == MVT::i32) {
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// Handle 32-bit sext immediates with LIS + addr mode.
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if (CN->getValueType(0) == MVT::i32 ||
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(int64_t)CN->getValue() == (int)CN->getValue()) {
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int Addr = (int)CN->getValue();
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// Otherwise, break this down into an LIS + disp.
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Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
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Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
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Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
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Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
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unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
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Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
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return true;
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}
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}
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