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The classes F4_3 and F4_4 have an `rd' operand that needs to be set.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7073 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2003-07-02 18:27:47 +00:00
parent a8fcdd8d04
commit bd272999dd
1 changed files with 3 additions and 0 deletions
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3
lib/Target/SparcV9/SparcV9_F4.td
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@ -80,11 +80,13 @@ class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
string name> : F4_condcc {
bits<5> rs2;
bits<5> rd;
set op = opVal;
set op3 = op3Val;
set cond = condVal;
set Name = name;
set Inst{29-25} = rd;
set Inst{13} = 0; // i bit
//set Inst{10-5} = dontcare;
set Inst{4-0} = rs2;
@ -99,6 +101,7 @@ class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
set op3 = op3Val;
set cond = condVal;
set Name = name;
set Inst{29-25} = rd;
set Inst{13} = 1; // i bit
set Inst{10-0} = sim11;
}