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R600/SI: Fix suspicious indexing

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The loop is over the operands of an instruction, and checks the
register with the sub reg index of the dest register. This probably
meant to be checking the sub reg index of the same operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223205 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-12-03 05:22:32 +00:00
parent cfde1fb5be
commit bd5f9f45d1
1 changed files with 7 additions and 5 deletions
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12
lib/Target/R600/SIFixSGPRCopies.cpp
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@ -219,11 +219,13 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
case AMDGPU::PHI: {
DEBUG(dbgs() << "Fixing PHI: " << MI);
for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
unsigned Reg = MI.getOperand(i).getReg();
const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg,
MI.getOperand(0).getSubReg());
MRI.constrainRegClass(Reg, RC);
for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
const MachineOperand &Op = MI.getOperand(i);
unsigned Reg = Op.getReg();
const TargetRegisterClass *RC
= inferRegClassFromDef(TRI, MRI, Reg, Op.getSubReg());
MRI.constrainRegClass(Op.getReg(), RC);
}
unsigned Reg = MI.getOperand(0).getReg();
const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg,