mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 03:29:40 +00:00
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -127,7 +127,6 @@ FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
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FunctionPass *createARMExpandPseudoPass();
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FunctionPass *createARMGlobalMergePass(const TargetLowering* tli);
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FunctionPass *createARMConstantIslandPass();
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FunctionPass *createNEONPreAllocPass();
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FunctionPass *createNEONMoveFixPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createThumb2SizeReductionPass();
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@ -44,6 +44,8 @@ namespace {
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void ExpandVLD(MachineBasicBlock::iterator &MBBI);
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void ExpandVST(MachineBasicBlock::iterator &MBBI);
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void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
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void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool IsExt, unsigned NumRegs);
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};
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char ARMExpandPseudo::ID = 0;
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}
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@ -326,7 +328,7 @@ static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
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D1 = TRI->getSubReg(Reg, ARM::dsub_3);
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D2 = TRI->getSubReg(Reg, ARM::dsub_5);
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D3 = TRI->getSubReg(Reg, ARM::dsub_7);
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}
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}
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}
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/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
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@ -414,10 +416,10 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
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if (NumRegs > 3)
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MIB.addReg(D3);
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MIB = AddDefaultPred(MIB);
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TransferImpOps(MI, MIB, MIB);
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if (SrcIsKill)
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// Add an implicit kill for the super-reg.
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(*MIB).addRegisterKilled(SrcReg, TRI, true);
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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}
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@ -500,6 +502,42 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
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MI.eraseFromParent();
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}
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/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
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/// register operands to real instructions with D register operands.
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void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool IsExt, unsigned NumRegs) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
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unsigned OpIdx = 0;
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// Transfer the destination register operand.
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MIB.addOperand(MI.getOperand(OpIdx++));
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if (IsExt)
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MIB.addOperand(MI.getOperand(OpIdx++));
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bool SrcIsKill = MI.getOperand(OpIdx).isKill();
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unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
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unsigned D0, D1, D2, D3;
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GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
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MIB.addReg(D0).addReg(D1);
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if (NumRegs > 2)
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MIB.addReg(D2);
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if (NumRegs > 3)
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MIB.addReg(D3);
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// Copy the other source register operand.
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MIB.addOperand(MI.getOperand(OpIdx));
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MIB = AddDefaultPred(MIB);
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if (SrcIsKill)
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// Add an implicit kill for the super-reg.
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(*MIB).addRegisterKilled(SrcReg, TRI, true);
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TransferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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}
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bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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@ -515,7 +553,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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ModifiedOp = false;
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break;
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case ARM::tLDRpci_pic:
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case ARM::tLDRpci_pic:
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case ARM::t2LDRpci_pic: {
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unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
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? ARM::tLDRpci : ARM::t2LDRpci;
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@ -765,6 +803,19 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::VST4LNq32Pseudo_UPD:
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ExpandLaneOp(MBBI);
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break;
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case ARM::VTBL2Pseudo:
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ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break;
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case ARM::VTBL3Pseudo:
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ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break;
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case ARM::VTBL4Pseudo:
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ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break;
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case ARM::VTBX2Pseudo:
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ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break;
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case ARM::VTBX3Pseudo:
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ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break;
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case ARM::VTBX4Pseudo:
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ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break;
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}
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if (ModifiedOp)
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@ -1353,17 +1353,10 @@ SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
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RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
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}
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// Now extract the D registers back out.
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SmallVector<SDValue, 6> Ops;
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if (IsExt)
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Ops.push_back(N->getOperand(1));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
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if (NumVecs > 2)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq));
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if (NumVecs > 3)
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Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq));
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Ops.push_back(RegSeq);
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Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
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Ops.push_back(getAL(CurDAG)); // predicate
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Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
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@ -2099,18 +2092,18 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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break;
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case Intrinsic::arm_neon_vtbl2:
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return SelectVTBL(N, false, 2, ARM::VTBL2);
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return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
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case Intrinsic::arm_neon_vtbl3:
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return SelectVTBL(N, false, 3, ARM::VTBL3);
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return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
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case Intrinsic::arm_neon_vtbl4:
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return SelectVTBL(N, false, 4, ARM::VTBL4);
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return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
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case Intrinsic::arm_neon_vtbx2:
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return SelectVTBL(N, true, 2, ARM::VTBX2);
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return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
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case Intrinsic::arm_neon_vtbx3:
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return SelectVTBL(N, true, 3, ARM::VTBX3);
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return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
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case Intrinsic::arm_neon_vtbx4:
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return SelectVTBL(N, true, 4, ARM::VTBX4);
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return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
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}
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break;
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}
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@ -1541,6 +1541,14 @@ class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
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list<Predicate> Predicates = [HasNEON];
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}
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class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr>
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: InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
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itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p));
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list<Predicate> Predicates = [HasNEON];
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}
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class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string dt, string asm, string cstr, list<dag> pattern>
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: NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
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@ -3838,6 +3838,13 @@ def VTBL4
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"vtbl", "8", "$dst, \\{$tbl1, $tbl2, $tbl3, $tbl4\\}, $src", "", []>;
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} // hasExtraSrcRegAllocReq = 1
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def VTBL2Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "">;
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def VTBL3Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "">;
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def VTBL4Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "">;
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// VTBX : Vector Table Extension
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def VTBX1
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: N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
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@ -3863,6 +3870,16 @@ def VTBX4
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"$orig = $dst", []>;
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} // hasExtraSrcRegAllocReq = 1
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def VTBX2Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
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IIC_VTBX2, "$orig = $dst">;
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def VTBX3Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
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IIC_VTBX3, "$orig = $dst">;
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def VTBX4Pseudo
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: PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
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IIC_VTBX4, "$orig = $dst">;
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//===----------------------------------------------------------------------===//
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// NEON instructions for single-precision FP math
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//===----------------------------------------------------------------------===//
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@ -104,9 +104,6 @@ bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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if (Subtarget.hasNEON())
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PM.add(createNEONPreAllocPass());
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// FIXME: temporarily disabling load / store optimization pass for Thumb1.
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if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass(true));
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@ -37,7 +37,6 @@ add_llvm_target(ARMCodeGen
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ARMTargetMachine.cpp
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ARMTargetObjectFile.cpp
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NEONMoveFix.cpp
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NEONPreAllocPass.cpp
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Thumb1InstrInfo.cpp
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Thumb1RegisterInfo.cpp
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Thumb2HazardRecognizer.cpp
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@ -1,268 +0,0 @@
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//===-- NEONPreAllocPass.cpp - Allocate adjacent NEON registers--*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "neon-prealloc"
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#include "ARM.h"
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#include "ARMInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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namespace {
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class NEONPreAllocPass : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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public:
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static char ID;
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NEONPreAllocPass() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "NEON register pre-allocation pass";
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}
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private:
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bool FormsRegSequence(MachineInstr *MI,
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unsigned FirstOpnd, unsigned NumRegs,
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unsigned Offset, unsigned Stride) const;
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bool PreAllocNEONRegisters(MachineBasicBlock &MBB);
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};
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char NEONPreAllocPass::ID = 0;
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}
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static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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unsigned &Offset, unsigned &Stride) {
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// Default to unit stride with no offset.
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Stride = 1;
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Offset = 0;
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switch (Opcode) {
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default:
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break;
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case ARM::VTBL2:
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FirstOpnd = 1;
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NumRegs = 2;
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return true;
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case ARM::VTBL3:
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FirstOpnd = 1;
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NumRegs = 3;
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return true;
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case ARM::VTBL4:
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FirstOpnd = 1;
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NumRegs = 4;
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return true;
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case ARM::VTBX2:
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FirstOpnd = 2;
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NumRegs = 2;
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return true;
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case ARM::VTBX3:
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FirstOpnd = 2;
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NumRegs = 3;
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return true;
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case ARM::VTBX4:
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FirstOpnd = 2;
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NumRegs = 4;
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return true;
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}
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return false;
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}
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bool
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NEONPreAllocPass::FormsRegSequence(MachineInstr *MI,
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unsigned FirstOpnd, unsigned NumRegs,
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unsigned Offset, unsigned Stride) const {
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MachineOperand &FMO = MI->getOperand(FirstOpnd);
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assert(FMO.isReg() && FMO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = FMO.getReg();
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(void)VirtReg;
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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unsigned LastSubIdx = 0;
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if (FMO.isDef()) {
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MachineInstr *RegSeq = 0;
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for (unsigned R = 0; R < NumRegs; ++R) {
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const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = MO.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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// Feeding into a REG_SEQUENCE.
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if (!MRI->hasOneNonDBGUse(VirtReg))
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return false;
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MachineInstr *UseMI = &*MRI->use_nodbg_begin(VirtReg);
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if (!UseMI->isRegSequence())
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return false;
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if (RegSeq && RegSeq != UseMI)
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return false;
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unsigned OpIdx = 1 + (Offset + R * Stride) * 2;
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if (UseMI->getOperand(OpIdx).getReg() != VirtReg)
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llvm_unreachable("Malformed REG_SEQUENCE instruction!");
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unsigned SubIdx = UseMI->getOperand(OpIdx + 1).getImm();
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if (LastSubIdx) {
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if (LastSubIdx != SubIdx-Stride)
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return false;
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} else {
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// Must start from dsub_0 or qsub_0.
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if (SubIdx != (ARM::dsub_0+Offset) &&
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SubIdx != (ARM::qsub_0+Offset))
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return false;
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}
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RegSeq = UseMI;
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LastSubIdx = SubIdx;
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}
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// In the case of vld3, etc., make sure the trailing operand of
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// REG_SEQUENCE is an undef.
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if (NumRegs == 3) {
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unsigned OpIdx = 1 + (Offset + 3 * Stride) * 2;
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const MachineOperand &MO = RegSeq->getOperand(OpIdx);
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unsigned VirtReg = MO.getReg();
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MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
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if (!DefMI || !DefMI->isImplicitDef())
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return false;
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}
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return true;
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}
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unsigned LastSrcReg = 0;
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SmallVector<unsigned, 4> SubIds;
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for (unsigned R = 0; R < NumRegs; ++R) {
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const MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
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unsigned VirtReg = MO.getReg();
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"expected a virtual register");
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// Extracting from a Q or QQ register.
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MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
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if (!DefMI || !DefMI->isCopy() || !DefMI->getOperand(1).getSubReg())
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return false;
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VirtReg = DefMI->getOperand(1).getReg();
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if (LastSrcReg && LastSrcReg != VirtReg)
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return false;
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LastSrcReg = VirtReg;
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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if (RC != ARM::QPRRegisterClass &&
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RC != ARM::QQPRRegisterClass &&
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RC != ARM::QQQQPRRegisterClass)
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return false;
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unsigned SubIdx = DefMI->getOperand(1).getSubReg();
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if (LastSubIdx) {
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if (LastSubIdx != SubIdx-Stride)
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return false;
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} else {
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// Must start from dsub_0 or qsub_0.
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if (SubIdx != (ARM::dsub_0+Offset) &&
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SubIdx != (ARM::qsub_0+Offset))
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return false;
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}
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SubIds.push_back(SubIdx);
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LastSubIdx = SubIdx;
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}
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// FIXME: Update the uses of EXTRACT_SUBREG from REG_SEQUENCE is
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// currently required for correctness. e.g.
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// %reg1041<def> = REG_SEQUENCE %reg1040<kill>, 5, %reg1035<kill>, 6
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// %reg1042<def> = EXTRACT_SUBREG %reg1041, 6
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// %reg1043<def> = EXTRACT_SUBREG %reg1041, 5
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// VST1q16 %reg1025<kill>, 0, %reg1043<kill>, %reg1042<kill>,
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// reg1042 and reg1043 should be replaced with reg1041:6 and reg1041:5
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// respectively.
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// We need to change how we model uses of REG_SEQUENCE.
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for (unsigned R = 0; R < NumRegs; ++R) {
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MachineOperand &MO = MI->getOperand(FirstOpnd + R);
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unsigned OldReg = MO.getReg();
|
||||
MachineInstr *DefMI = MRI->getVRegDef(OldReg);
|
||||
assert(DefMI->isCopy());
|
||||
MO.setReg(LastSrcReg);
|
||||
MO.setSubReg(SubIds[R]);
|
||||
MO.setIsKill(false);
|
||||
// Delete the EXTRACT_SUBREG if its result is now dead.
|
||||
if (MRI->use_empty(OldReg))
|
||||
DefMI->eraseFromParent();
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
|
||||
bool Modified = false;
|
||||
|
||||
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
||||
for (; MBBI != E; ++MBBI) {
|
||||
MachineInstr *MI = &*MBBI;
|
||||
unsigned FirstOpnd, NumRegs, Offset, Stride;
|
||||
if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
|
||||
continue;
|
||||
if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
|
||||
continue;
|
||||
|
||||
MachineBasicBlock::iterator NextI = llvm::next(MBBI);
|
||||
for (unsigned R = 0; R < NumRegs; ++R) {
|
||||
MachineOperand &MO = MI->getOperand(FirstOpnd + R);
|
||||
assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
|
||||
unsigned VirtReg = MO.getReg();
|
||||
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
|
||||
"expected a virtual register");
|
||||
|
||||
// For now, just assign a fixed set of adjacent registers.
|
||||
// This leaves plenty of room for future improvements.
|
||||
static const unsigned NEONDRegs[] = {
|
||||
ARM::D0, ARM::D1, ARM::D2, ARM::D3,
|
||||
ARM::D4, ARM::D5, ARM::D6, ARM::D7
|
||||
};
|
||||
MO.setReg(NEONDRegs[Offset + R * Stride]);
|
||||
|
||||
if (MO.isUse()) {
|
||||
// Insert a copy from VirtReg.
|
||||
BuildMI(MBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),MO.getReg())
|
||||
.addReg(VirtReg, getKillRegState(MO.isKill()));
|
||||
MO.setIsKill();
|
||||
} else if (MO.isDef() && !MO.isDead()) {
|
||||
// Add a copy to VirtReg.
|
||||
BuildMI(MBB, NextI, DebugLoc(), TII->get(TargetOpcode::COPY), VirtReg)
|
||||
.addReg(MO.getReg());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return Modified;
|
||||
}
|
||||
|
||||
bool NEONPreAllocPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
TII = MF.getTarget().getInstrInfo();
|
||||
MRI = &MF.getRegInfo();
|
||||
|
||||
bool Modified = false;
|
||||
for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
|
||||
++MFI) {
|
||||
MachineBasicBlock &MBB = *MFI;
|
||||
Modified |= PreAllocNEONRegisters(MBB);
|
||||
}
|
||||
|
||||
return Modified;
|
||||
}
|
||||
|
||||
/// createNEONPreAllocPass - returns an instance of the NEON register
|
||||
/// pre-allocation pass.
|
||||
FunctionPass *llvm::createNEONPreAllocPass() {
|
||||
return new NEONPreAllocPass();
|
||||
}
|
Loading…
Reference in New Issue
Block a user