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Codegen (Reg|imm)+&GV as an LEA, because we cannot put it into the immediate field
of an ADDri (due to current restrictions on MachineOperand :( ). This allows us to generate: leal Data+16000, %edx instead of: movl $Data, %edx addl $16000, %edx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19420 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1027,11 +1027,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (!SelectAddress(N.getOperand(0), AM) &&
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!SelectAddress(N.getOperand(1), AM)) {
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// If this is not just an add, emit the LEA. For a simple add (like
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// reg+reg or reg+imm), we just emit an add. If might be a good idea to
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// reg+reg or reg+imm), we just emit an add. It might be a good idea to
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// leave this as LEA, then peephole it to 'ADD' after two address elim
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// happens.
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if (AM.Scale != 1 || AM.BaseType == X86AddressMode::FrameIndexBase ||
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AM.Base.Reg && AM.IndexReg && (AM.Disp || AM.GV)) {
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AM.GV || (AM.Base.Reg && AM.IndexReg && AM.Disp)) {
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addFullAddress(BuildMI(BB, X86::LEA32r, 4, Result), AM);
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return Result;
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}
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