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Codegen (Reg|imm)+&GV as an LEA, because we cannot put it into the immediate field

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of an ADDri (due to current restrictions on MachineOperand :( ).  This allows
us to generate:

        leal Data+16000, %edx

instead of:

        movl $Data, %edx
        addl $16000, %edx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19420 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-09 20:20:29 +00:00
parent abd2182875
commit bd9f0eefb2
1 changed files with 2 additions and 2 deletions
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4
lib/Target/X86/X86ISelPattern.cpp
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@ -1027,11 +1027,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
if (!SelectAddress(N.getOperand(0), AM) &&
!SelectAddress(N.getOperand(1), AM)) {
// If this is not just an add, emit the LEA. For a simple add (like
// reg+reg or reg+imm), we just emit an add. If might be a good idea to
// reg+reg or reg+imm), we just emit an add. It might be a good idea to
// leave this as LEA, then peephole it to 'ADD' after two address elim
// happens.
if (AM.Scale != 1 || AM.BaseType == X86AddressMode::FrameIndexBase ||
AM.Base.Reg && AM.IndexReg && (AM.Disp || AM.GV)) {
AM.GV || (AM.Base.Reg && AM.IndexReg && AM.Disp)) {
addFullAddress(BuildMI(BB, X86::LEA32r, 4, Result), AM);
return Result;
}