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Add sub reg-reg pattern

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75916 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 13:32:16 +00:00
parent b573f99ab7
commit bdc9081693
3 changed files with 20 additions and 0 deletions
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6
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -77,6 +77,12 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
}
// FIXME: provide patterns for masked or-with-imm
// FIXME: Provide proper encoding!
def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"sgr\t{$dst, $src2}",
[(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
// FIXME: Provide proper encoding!
def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),

7
test/CodeGen/SystemZ/02-RetSub.ll Normal file
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@ -0,0 +1,7 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = sub i64 %a, %b
ret i64 %c
}

7
test/CodeGen/SystemZ/02-RetSubImm.ll Normal file
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@ -0,0 +1,7 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = sub i64 %a, 1
ret i64 %c
}