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[X86, AVX] instcombine common cases of vperm2* intrinsics into shuffles
vperm2* intrinsics are just shuffles. In a few special cases, they're not even shuffles. Optimizing intrinsics in InstCombine is better than handling this in the front-end for at least two reasons: 1. Optimizing custom-written SSE intrinsic code at -O0 makes vector coders really angry (and so I have regrets about some patches from last week). 2. Doing mask conversion logic in header files is hard to write and subsequently read. There are a couple of TODOs in this patch to complete this optimization. Differential Revision: http://reviews.llvm.org/D8486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232852 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel
parent
e0e1c1d94d
commit
be9ee96926
@ -197,6 +197,57 @@ Instruction *InstCombiner::SimplifyMemSet(MemSetInst *MI) {
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return nullptr;
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}
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/// The shuffle mask for a perm2*128 selects any two halves of two 256-bit
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/// source vectors, unless a zero bit is set. If a zero bit is set,
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/// then ignore that half of the mask and clear that half of the vector.
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static Value *SimplifyX86vperm2(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder) {
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if (auto CInt = dyn_cast<ConstantInt>(II.getArgOperand(2))) {
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VectorType *VecTy = cast<VectorType>(II.getType());
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uint8_t Imm = CInt->getZExtValue();
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// The immediate permute control byte looks like this:
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// [1:0] - select 128 bits from sources for low half of destination
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// [2] - ignore
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// [3] - zero low half of destination
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// [5:4] - select 128 bits from sources for high half of destination
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// [6] - ignore
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// [7] - zero high half of destination
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if ((Imm & 0x88) == 0x88) {
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// If both zero mask bits are set, this was just a weird way to
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// generate a zero vector.
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return ConstantAggregateZero::get(VecTy);
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}
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// TODO: If a single zero bit is set, replace one of the source operands
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// with a zero vector and use the same mask generation logic as below.
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if ((Imm & 0x88) == 0x00) {
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// If neither zero mask bit is set, this is a simple shuffle.
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unsigned NumElts = VecTy->getNumElements();
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unsigned HalfSize = NumElts / 2;
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unsigned HalfBegin;
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SmallVector<int, 8> ShuffleMask(NumElts);
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// Permute low half of result.
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HalfBegin = (Imm & 0x3) * HalfSize;
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for (unsigned i = 0; i != HalfSize; ++i)
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ShuffleMask[i] = HalfBegin + i;
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// Permute high half of result.
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HalfBegin = ((Imm >> 4) & 0x3) * HalfSize;
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for (unsigned i = HalfSize; i != NumElts; ++i)
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ShuffleMask[i] = HalfBegin + i - HalfSize;
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Value *Op0 = II.getArgOperand(0);
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Value *Op1 = II.getArgOperand(1);
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return Builder.CreateShuffleVector(Op0, Op1, ShuffleMask);
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}
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}
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return nullptr;
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}
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/// visitCallInst - CallInst simplification. This mostly only handles folding
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/// of intrinsic instructions. For normal calls, it allows visitCallSite to do
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/// the heavy lifting.
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@ -904,6 +955,14 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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return ReplaceInstUsesWith(CI, Shuffle);
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}
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case Intrinsic::x86_avx_vperm2f128_pd_256:
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case Intrinsic::x86_avx_vperm2f128_ps_256:
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case Intrinsic::x86_avx_vperm2f128_si_256:
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// TODO: Add the AVX2 version of this instruction.
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if (Value *V = SimplifyX86vperm2(*II, *Builder))
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return ReplaceInstUsesWith(*II, V);
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break;
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case Intrinsic::ppc_altivec_vperm:
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// Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
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// Note that ppc_altivec_vperm has a big-endian bias, so when creating
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236
test/Transforms/InstCombine/x86-vperm2.ll
Normal file
236
test/Transforms/InstCombine/x86-vperm2.ll
Normal file
@ -0,0 +1,236 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; This should never happen, but make sure we don't crash handling a non-constant immediate byte.
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define <4 x double> @perm2pd_non_const_imm(<4 x double> %a0, <4 x double> %a1, i8 %b) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %b)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_non_const_imm
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; CHECK-NEXT: call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %b)
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; CHECK-NEXT: ret <4 x double>
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}
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; In the following 3 tests, both zero mask bits of the immediate are set.
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define <4 x double> @perm2pd_0x88(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 136)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x88
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; CHECK-NEXT: ret <4 x double> zeroinitializer
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}
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define <8 x float> @perm2ps_0x88(<8 x float> %a0, <8 x float> %a1) {
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%res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 136)
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ret <8 x float> %res
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; CHECK-LABEL: @perm2ps_0x88
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; CHECK-NEXT: ret <8 x float> zeroinitializer
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}
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define <8 x i32> @perm2si_0x88(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32> %a0, <8 x i32> %a1, i8 136)
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ret <8 x i32> %res
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; CHECK-LABEL: @perm2si_0x88
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; CHECK-NEXT: ret <8 x i32> zeroinitializer
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}
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; The other control bits are ignored when zero mask bits of the immediate are set.
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define <4 x double> @perm2pd_0xff(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 255)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0xff
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; CHECK-NEXT: ret <4 x double> zeroinitializer
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}
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; The following 16 tests are simple shuffles, except for 2 cases where we can just return one of the
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; source vectors. Verify that we generate the right shuffle masks and undef source operand where possible..
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define <4 x double> @perm2pd_0x00(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 0)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x00
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x01(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 1)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x01
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x02(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 2)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x02
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x03(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 3)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x03
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x10(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 16)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x10
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; CHECK-NEXT: ret <4 x double> %a0
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}
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define <4 x double> @perm2pd_0x11(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 17)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x11
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x12(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 18)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x12
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x13(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 19)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x13
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x20(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 32)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x20
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x21(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 33)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x21
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x22(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 34)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x22
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x23(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 35)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x23
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a1, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x30(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 48)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x30
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x31(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 49)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x31
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a0, <4 x double> %a1, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> %1
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}
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define <4 x double> @perm2pd_0x32(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 50)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x32
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; CHECK-NEXT: ret <4 x double> %a1
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}
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define <4 x double> @perm2pd_0x33(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 51)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x33
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; CHECK-NEXT: %1 = shufflevector <4 x double> %a1, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x double> %1
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}
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; Confirm that a mask for 32-bit elements is also correct.
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define <8 x float> @perm2ps_0x31(<8 x float> %a0, <8 x float> %a1) {
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%res = call <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float> %a0, <8 x float> %a1, i8 49)
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ret <8 x float> %res
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; CHECK-LABEL: @perm2ps_0x31
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; CHECK-NEXT: %1 = shufflevector <8 x float> %a0, <8 x float> %a1, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
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; CHECK-NEXT: ret <8 x float> %1
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}
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; Confirm that when a single zero mask bit is set, we do nothing.
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define <4 x double> @perm2pd_0x83(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 131)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x83
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; CHECK-NEXT: call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 -125)
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; CHECK-NEXT: ret <4 x double>
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}
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; Confirm that when the other zero mask bit is set, we do nothing. Also confirm that an ignored bit has no effect.
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define <4 x double> @perm2pd_0x48(<4 x double> %a0, <4 x double> %a1) {
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%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 72)
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ret <4 x double> %res
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; CHECK-LABEL: @perm2pd_0x48
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; CHECK-NEXT: call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 72)
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; CHECK-NEXT: ret <4 x double>
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}
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declare <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
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declare <8 x float> @llvm.x86.avx.vperm2f128.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
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declare <8 x i32> @llvm.x86.avx.vperm2f128.si.256(<8 x i32>, <8 x i32>, i8) nounwind readnone
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