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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Print more immediates in hex format
Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
dd368a8755
commit
bec5c611e1
@ -37,6 +37,18 @@ class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
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def u32imm : Operand<i32> {
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let PrintMethod = "printU32ImmOperand";
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}
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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}
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def u8imm : Operand<i8> {
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let PrintMethod = "printU8ImmOperand";
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}
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//===----------------------------------------------------------------------===//
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// PatLeafs for floating-point comparisons
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//===----------------------------------------------------------------------===//
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@ -12,6 +12,8 @@
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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@ -23,6 +25,21 @@ void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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printAnnotation(OS, Annot);
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}
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void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
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}
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void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
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}
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void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
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}
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void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
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switch (reg) {
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case AMDGPU::VCC:
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@ -93,6 +110,28 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
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O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
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}
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void AMDGPUInstPrinter::printImmediate(uint32_t Imm, raw_ostream &O) {
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int32_t SImm = static_cast<int32_t>(Imm);
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if (SImm >= -16 && SImm <= 64) {
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O << SImm;
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return;
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}
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if (Imm == FloatToBits(1.0f) ||
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Imm == FloatToBits(-1.0f) ||
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Imm == FloatToBits(0.5f) ||
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Imm == FloatToBits(-0.5f) ||
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Imm == FloatToBits(2.0f) ||
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Imm == FloatToBits(-2.0f) ||
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Imm == FloatToBits(4.0f) ||
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Imm == FloatToBits(-4.0f)) {
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O << BitsToFloat(Imm);
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return;
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}
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O << formatHex(static_cast<uint64_t>(Imm));
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}
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void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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@ -108,7 +147,7 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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break;
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}
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} else if (Op.isImm()) {
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O << Op.getImm();
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printImmediate(Op.getImm(), O);
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} else if (Op.isFPImm()) {
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O << Op.getFPImm();
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} else if (Op.isExpr()) {
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@ -32,7 +32,11 @@ public:
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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private:
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void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printRegOperand(unsigned RegNo, raw_ostream &O);
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void printImmediate(uint32_t Imm, raw_ostream &O);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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@ -222,7 +222,7 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass baseClass,
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RegisterClass dstClass> {
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def _IMM : SMRD <
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op, 1, (outs dstClass:$dst),
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(ins baseClass:$sbase, i32imm:$offset),
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(ins baseClass:$sbase, u32imm:$offset),
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asm#" $dst, $sbase, $offset", []
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>;
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@ -404,7 +404,7 @@ class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
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class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
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op,
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(outs regClass:$vdst),
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(ins i1imm:$gds, VReg_32:$addr, i16imm:$offset),
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(ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
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asm#" $vdst, $addr, $offset, [M0]",
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[]> {
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let data0 = 0;
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@ -416,7 +416,7 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
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class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
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op,
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(outs regClass:$vdst),
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(ins i1imm:$gds, VReg_32:$addr, i8imm:$offset0, i8imm:$offset1),
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(ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
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asm#" $gds, $vdst, $addr, $offset0, $offset1, [M0]",
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[]> {
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let data0 = 0;
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@ -428,7 +428,7 @@ class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
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class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
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op,
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(outs),
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(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, i16imm:$offset),
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(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
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asm#" $addr, $data0, $offset [M0]",
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[]> {
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let data1 = 0;
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@ -440,7 +440,7 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
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class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
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op,
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(outs),
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(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, i8imm:$offset0, i8imm:$offset1),
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(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u8imm:$offset0, u8imm:$offset1),
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asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
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[]> {
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let mayStore = 1;
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@ -451,7 +451,7 @@ class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A
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class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
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op,
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(outs rc:$vdst),
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(ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
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(ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, u16imm:$offset),
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asm#" $vdst, $addr, $data0, $offset, [M0]",
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[]> {
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@ -463,7 +463,7 @@ class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
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class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs),
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(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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(ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
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SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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@ -482,7 +482,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
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let offen = 0, idxen = 0 in {
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def _OFFSET : MUBUF <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_32:$vaddr,
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i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
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u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
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i1imm:$slc, i1imm:$tfe),
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asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
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}
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@ -498,7 +498,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
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let offen = 0, idxen = 1 in {
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def _IDXEN : MUBUF <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_32:$vaddr,
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i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
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u16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
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i1imm:$slc, i1imm:$tfe),
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asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
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}
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@ -514,7 +514,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
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let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
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def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
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(ins SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
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asm#" $vdata, $srsrc + $vaddr + $offset", []>;
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}
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}
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@ -522,7 +522,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
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class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
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MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
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i16imm:$offset),
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u16imm:$offset),
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name#" $vdata, $srsrc + $vaddr + $offset",
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[]> {
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@ -543,7 +543,7 @@ class MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
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class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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(ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
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i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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@ -33,7 +33,7 @@ entry:
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; CHECK-LABEL: @local_address_gep_const_offset
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VPTR]], 4,
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VPTR]], 0x4,
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define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = getelementptr i32 addrspace(3)* %in, i32 1
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@ -44,7 +44,7 @@ entry:
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; Offset too large, can't fold into 16-bit immediate offset.
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; CHECK-LABEL: @local_address_gep_large_const_offset
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 65540
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: DS_READ_B32 [[VPTR]]
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define void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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@ -119,7 +119,7 @@ define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32
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; CHECK-LABEL: @local_address_gep_const_offset_store
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: V_MOV_B32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; CHECK: DS_WRITE_B32 [[VPTR]], [[VAL]], 4
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; CHECK: DS_WRITE_B32 [[VPTR]], [[VAL]], 0x4
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define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
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%gep = getelementptr i32 addrspace(3)* %out, i32 1
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store i32 %val, i32 addrspace(3)* %gep, align 4
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@ -128,7 +128,7 @@ define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %v
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; Offset too large, can't fold into 16-bit immediate offset.
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; CHECK-LABEL: @local_address_gep_large_const_offset_store
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 65540
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; CHECK: S_ADD_I32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: DS_WRITE_B32 [[VPTR]], v{{[0-9]+}}, 0
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define void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
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@ -1,8 +1,8 @@
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; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; SI-CHECK: @f64_kernel_arg
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; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 9
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; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 11
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; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 0x9
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; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 0xb
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; SI-CHECK: BUFFER_STORE_DWORDX2
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define void @f64_kernel_arg(double addrspace(1)* %out, double %in) {
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entry:
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@ -10,8 +10,8 @@
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; CHECK-LABEL: @do_as_ptr_calcs:
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; CHECK: S_LOAD_DWORD [[SREG1:s[0-9]+]],
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; CHECK: V_MOV_B32_e32 [[VREG1:v[0-9]+]], [[SREG1]]
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VREG1]], 20
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; CHECK: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}}, 12
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; CHECK: DS_READ_B32 v{{[0-9]+}}, [[VREG1]], 0x14
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; CHECK: DS_READ_B32 v{{[0-9]+}}, v{{[0-9]+}}, 0xc
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define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind {
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entry:
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%x = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0
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@ -1,7 +1,7 @@
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; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
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; CHECK: @fconst_f64
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; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 1075052544
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; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0x40140000
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; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0
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define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
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@ -3,7 +3,7 @@
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define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
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; CHECK-LABEL: @use_gep_address_space:
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; CHECK: V_MOV_B32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: DS_WRITE_B32 [[PTR]], v{{[0-9]+}}, 64
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; CHECK: DS_WRITE_B32 [[PTR]], v{{[0-9]+}}, 0x40
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%p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16
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store i32 99, i32 addrspace(3)* %p
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ret void
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@ -1,7 +1,7 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: @infinite_loop:
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; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 999
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; SI: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x3e7
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; SI: BB0_1:
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; SI: BUFFER_STORE_DWORD [[REG]]
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; SI: S_WAITCNT vmcnt(0) expcnt(0)
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@ -17,7 +17,7 @@ entry:
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; EG-CHECK-LABEL: @i8_zext_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i8_zext_arg
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
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entry:
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@ -29,7 +29,7 @@ entry:
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; EG-CHECK-LABEL: @i8_sext_arg
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; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
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; SI-CHECK-LABEL: @i8_sext_arg
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
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; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
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define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
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entry:
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@ -53,7 +53,7 @@ entry:
|
||||
; EG-CHECK-LABEL: @i16_zext_arg
|
||||
; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
; SI-CHECK-LABEL: @i16_zext_arg
|
||||
; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
|
||||
; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
|
||||
|
||||
define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
|
||||
entry:
|
||||
@ -65,7 +65,7 @@ entry:
|
||||
; EG-CHECK-LABEL: @i16_sext_arg
|
||||
; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
; SI-CHECK-LABEL: @i16_sext_arg
|
||||
; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
|
||||
; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
|
||||
|
||||
define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
|
||||
entry:
|
||||
@ -77,7 +77,7 @@ entry:
|
||||
; EG-CHECK-LABEL: @i32_arg
|
||||
; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z
|
||||
; SI-CHECK-LABEL: @i32_arg
|
||||
; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
|
||||
; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
|
||||
define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind {
|
||||
entry:
|
||||
store i32 %in, i32 addrspace(1)* %out, align 4
|
||||
@ -87,7 +87,7 @@ entry:
|
||||
; EG-CHECK-LABEL: @f32_arg
|
||||
; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z
|
||||
; SI-CHECK-LABEL: @f32_arg
|
||||
; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11
|
||||
; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 0xb
|
||||
define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind {
|
||||
entry:
|
||||
store float %in, float addrspace(1)* %out, align 4
|
||||
@ -122,7 +122,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
|
||||
; SI-CHECK-LABEL: @v2i32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 11
|
||||
; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
|
||||
define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind {
|
||||
entry:
|
||||
store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4
|
||||
@ -133,7 +133,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W
|
||||
; SI-CHECK-LABEL: @v2f32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 11
|
||||
; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xb
|
||||
define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind {
|
||||
entry:
|
||||
store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4
|
||||
@ -166,7 +166,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; SI-CHECK-LABEL: @v3i32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 13
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
|
||||
define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind {
|
||||
entry:
|
||||
store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4
|
||||
@ -178,7 +178,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; SI-CHECK-LABEL: @v3f32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 13
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
|
||||
define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind {
|
||||
entry:
|
||||
store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4
|
||||
@ -223,7 +223,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
; SI-CHECK-LABEL: @v4i32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 13
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
|
||||
define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind {
|
||||
entry:
|
||||
store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
|
||||
@ -236,7 +236,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
; SI-CHECK-LABEL: @v4f32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 13
|
||||
; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
|
||||
define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
|
||||
entry:
|
||||
store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
|
||||
@ -300,7 +300,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
|
||||
; SI-CHECK-LABEL: @v8i32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 17
|
||||
; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
|
||||
define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind {
|
||||
entry:
|
||||
store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4
|
||||
@ -317,7 +317,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X
|
||||
; SI-CHECK-LABEL: @v8f32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 17
|
||||
; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
|
||||
define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind {
|
||||
entry:
|
||||
store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4
|
||||
@ -422,7 +422,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
|
||||
; SI-CHECK-LABEL: @v16i32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 25
|
||||
; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
|
||||
define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind {
|
||||
entry:
|
||||
store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4
|
||||
@ -447,7 +447,7 @@ entry:
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W
|
||||
; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X
|
||||
; SI-CHECK-LABEL: @v16f32_arg
|
||||
; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 25
|
||||
; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
|
||||
define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind {
|
||||
entry:
|
||||
store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: @test1
|
||||
;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 32, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 0x20, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
define void @test1(i32 %a1, i32 %vaddr) #0 {
|
||||
%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
|
||||
call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
|
||||
@ -11,7 +11,7 @@ define void @test1(i32 %a1, i32 %vaddr) #0 {
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @test2
|
||||
;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 24, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 0x18, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
define void @test2(i32 %a1, i32 %vaddr) #0 {
|
||||
%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
|
||||
call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
|
||||
@ -21,7 +21,7 @@ define void @test2(i32 %a1, i32 %vaddr) #0 {
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @test3
|
||||
;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 16, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 0x10, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
define void @test3(i32 %a1, i32 %vaddr) #0 {
|
||||
%vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
|
||||
call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata,
|
||||
@ -31,7 +31,7 @@ define void @test3(i32 %a1, i32 %vaddr) #0 {
|
||||
}
|
||||
|
||||
;CHECK-LABEL: @test4
|
||||
;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 0x8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
|
||||
define void @test4(i32 %vdata, i32 %vaddr) #0 {
|
||||
call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,
|
||||
i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
|
||||
|
||||
; SI-LABEL: @local_i32_load
|
||||
; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 28, [M0]
|
||||
; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
|
||||
; SI: BUFFER_STORE_DWORD [[REG]],
|
||||
define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i32 addrspace(3)* %in, i32 7
|
||||
@ -11,7 +11,7 @@ define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounw
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i32_load_0_offset
|
||||
; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0, [M0]
|
||||
; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; SI: BUFFER_STORE_DWORD [[REG]],
|
||||
define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
|
||||
%val = load i32 addrspace(3)* %in, align 4
|
||||
@ -21,7 +21,7 @@ define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %
|
||||
|
||||
; SI-LABEL: @local_i8_load_i16_max_offset
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, -1, [M0]
|
||||
; SI: DS_READ_U8 [[REG:v[0-9]+]], {{v[0-9]+}}, 0xffff, [M0]
|
||||
; SI: BUFFER_STORE_BYTE [[REG]],
|
||||
define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i8 addrspace(3)* %in, i32 65535
|
||||
@ -31,9 +31,9 @@ define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i8_load_over_i16_max_offset
|
||||
; SI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 65536
|
||||
; SI: S_ADD_I32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
|
||||
; SI: V_MOV_B32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
|
||||
; SI: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0, [M0]
|
||||
; SI: DS_READ_U8 [[REG:v[0-9]+]], [[VREGADDR]], 0x0, [M0]
|
||||
; SI: BUFFER_STORE_BYTE [[REG]],
|
||||
define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i8 addrspace(3)* %in, i32 65536
|
||||
@ -44,7 +44,7 @@ define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspa
|
||||
|
||||
; SI-LABEL: @local_i64_load
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 56, [M0]
|
||||
; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %in, i32 7
|
||||
@ -54,7 +54,7 @@ define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounw
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_i64_load_0_offset
|
||||
; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0, [M0]
|
||||
; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
|
||||
%val = load i64 addrspace(3)* %in, align 8
|
||||
@ -64,7 +64,7 @@ define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %
|
||||
|
||||
; SI-LABEL: @local_f64_load
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 56, [M0]
|
||||
; SI: DS_READ_B64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}}, 0x38, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr double addrspace(3)* %in, i32 7
|
||||
@ -74,7 +74,7 @@ define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in)
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_f64_load_0_offset
|
||||
; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0, [M0]
|
||||
; SI: DS_READ_B64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, 0x0, [M0]
|
||||
; SI: BUFFER_STORE_DWORDX2 [[REG]],
|
||||
define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
|
||||
%val = load double addrspace(3)* %in, align 8
|
||||
@ -84,7 +84,7 @@ define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace
|
||||
|
||||
; SI-LABEL: @local_i64_store
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 56 [M0]
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
|
||||
define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %out, i32 7
|
||||
store i64 5678, i64 addrspace(3)* %gep, align 8
|
||||
@ -93,7 +93,7 @@ define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
|
||||
|
||||
; SI-LABEL: @local_i64_store_0_offset
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0 [M0]
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
|
||||
store i64 1234, i64 addrspace(3)* %out, align 8
|
||||
ret void
|
||||
@ -101,7 +101,7 @@ define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
|
||||
|
||||
; SI-LABEL: @local_f64_store
|
||||
; SI-NOT: ADD
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 56 [M0]
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x38 [M0]
|
||||
define void @local_f64_store(double addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr double addrspace(3)* %out, i32 7
|
||||
store double 16.0, double addrspace(3)* %gep, align 8
|
||||
@ -109,7 +109,7 @@ define void @local_f64_store(double addrspace(3)* %out) nounwind {
|
||||
}
|
||||
|
||||
; SI-LABEL: @local_f64_store_0_offset
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0 [M0]
|
||||
; SI: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
|
||||
store double 20.0, double addrspace(3)* %out, align 8
|
||||
ret void
|
||||
@ -117,8 +117,8 @@ define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
|
||||
|
||||
; SI-LABEL: @local_v2i64_store
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 120 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 112 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x78 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x70 [M0]
|
||||
define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
|
||||
store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
|
||||
@ -127,8 +127,8 @@ define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
|
||||
; SI-LABEL: @local_v2i64_store_0_offset
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
|
||||
ret void
|
||||
@ -136,10 +136,10 @@ define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
|
||||
; SI-LABEL: @local_v4i64_store
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 248 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 240 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 232 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 224 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xf0 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0xe0 [M0]
|
||||
define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
|
||||
store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
|
||||
@ -148,10 +148,10 @@ define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
|
||||
; SI-LABEL: @local_v4i64_store_0_offset
|
||||
; SI-NOT: ADD
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 24 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 16 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x18 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x10 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x8 [M0]
|
||||
; SI-DAG: DS_WRITE_B64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, 0x0 [M0]
|
||||
define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
|
||||
ret void
|
||||
|
||||
@ -28,8 +28,8 @@
|
||||
; constant offsets.
|
||||
; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
|
||||
; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
|
||||
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 16
|
||||
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0,
|
||||
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]], 0x10
|
||||
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]], 0x0,
|
||||
|
||||
define void @local_memory_two_objects(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
|
||||
; MUBUF load with an immediate byte offset that fits into 12-bits
|
||||
; CHECK-LABEL: @mubuf_load0
|
||||
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4 ; encoding: [0x04,0x80
|
||||
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0x4 ; encoding: [0x04,0x80
|
||||
define void @mubuf_load0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(1)* %in, i64 1
|
||||
@ -17,7 +17,7 @@ entry:
|
||||
|
||||
; MUBUF load with the largest possible immediate offset
|
||||
; CHECK-LABEL: @mubuf_load1
|
||||
; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4095 ; encoding: [0xff,0x8f
|
||||
; CHECK: BUFFER_LOAD_UBYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0xfff ; encoding: [0xff,0x8f
|
||||
define void @mubuf_load1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
|
||||
entry:
|
||||
%0 = getelementptr i8 addrspace(1)* %in, i64 4095
|
||||
@ -28,7 +28,7 @@ entry:
|
||||
|
||||
; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
|
||||
; CHECK-LABEL: @mubuf_load2
|
||||
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0 ; encoding: [0x00,0x80
|
||||
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0x0 ; encoding: [0x00,0x80
|
||||
define void @mubuf_load2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(1)* %in, i64 1024
|
||||
@ -40,7 +40,7 @@ entry:
|
||||
; MUBUF load with a 12-bit immediate offset and a register offset
|
||||
; CHECK-LABEL: @mubuf_load3
|
||||
; CHECK-NOT: ADD
|
||||
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4 ; encoding: [0x04,0x80
|
||||
; CHECK: BUFFER_LOAD_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0x4 ; encoding: [0x04,0x80
|
||||
define void @mubuf_load3(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i64 %offset) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(1)* %in, i64 %offset
|
||||
@ -56,7 +56,7 @@ entry:
|
||||
|
||||
; MUBUF store with an immediate byte offset that fits into 12-bits
|
||||
; CHECK-LABEL: @mubuf_store0
|
||||
; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4 ; encoding: [0x04,0x80
|
||||
; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0x4 ; encoding: [0x04,0x80
|
||||
define void @mubuf_store0(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(1)* %out, i64 1
|
||||
@ -66,7 +66,7 @@ entry:
|
||||
|
||||
; MUBUF store with the largest possible immediate offset
|
||||
; CHECK-LABEL: @mubuf_store1
|
||||
; CHECK: BUFFER_STORE_BYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4095 ; encoding: [0xff,0x8f
|
||||
; CHECK: BUFFER_STORE_BYTE v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0xfff ; encoding: [0xff,0x8f
|
||||
|
||||
define void @mubuf_store1(i8 addrspace(1)* %out) {
|
||||
entry:
|
||||
@ -77,7 +77,7 @@ entry:
|
||||
|
||||
; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
|
||||
; CHECK-LABEL: @mubuf_store2
|
||||
; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0 ; encoding: [0x00,0x80
|
||||
; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0x0 ; encoding: [0x00,0x80
|
||||
define void @mubuf_store2(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(1)* %out, i64 1024
|
||||
@ -88,7 +88,7 @@ entry:
|
||||
; MUBUF store with a 12-bit immediate offset and a register offset
|
||||
; CHECK-LABEL: @mubuf_store3
|
||||
; CHECK-NOT: ADD
|
||||
; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 4 ; encoding: [0x04,0x80
|
||||
; CHECK: BUFFER_STORE_DWORD v{{[0-9]}}, s[{{[0-9]:[0-9]}}] + v[{{[0-9]:[0-9]}}] + 0x4 ; encoding: [0x04,0x80
|
||||
define void @mubuf_store3(i32 addrspace(1)* %out, i64 %offset) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(1)* %out, i64 %offset
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK: V_MOV_B32_e32 v{{[0-9]+}}, -1431655765
|
||||
;CHECK: V_MOV_B32_e32 v{{[0-9]+}}, 0xaaaaaaab
|
||||
;CHECK: V_MUL_HI_U32 v0, {{[sv][0-9]+}}, {{v[0-9]+}}
|
||||
;CHECK-NEXT: V_LSHRREV_B32_e32 v0, 1, v0
|
||||
|
||||
|
||||
@ -89,8 +89,8 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a,
|
||||
}
|
||||
|
||||
; SI-LABEL: @vector_or_i64_loadimm
|
||||
; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], -545810305
|
||||
; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 5231
|
||||
; SI-DAG: S_MOV_B32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f
|
||||
; SI-DAG: S_MOV_B32 [[HI_S_IMM:s[0-9]+]], 0x146f
|
||||
; SI-DAG: BUFFER_LOAD_DWORDX2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
|
||||
; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
|
||||
; SI-DAG: V_OR_B32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]]
|
||||
|
||||
@ -119,7 +119,7 @@ for.end:
|
||||
; R600-CHECK: *
|
||||
; R600-CHECK: MOVA_INT
|
||||
|
||||
; SI-CHECK: V_MOV_B32_e32 v{{[0-9]}}, 65536
|
||||
; SI-CHECK: V_MOV_B32_e32 v{{[0-9]}}, 0x10000
|
||||
; SI-CHECK: V_MOVRELS_B32_e32
|
||||
define void @short_array(i32 addrspace(1)* %out, i32 %index) {
|
||||
entry:
|
||||
@ -142,7 +142,7 @@ entry:
|
||||
; R600-CHECK: *
|
||||
; R600-CHECK-NEXT: MOVA_INT
|
||||
|
||||
; SI-CHECK: V_OR_B32_e32 v{{[0-9]}}, 256
|
||||
; SI-CHECK: V_OR_B32_e32 v{{[0-9]}}, 0x100
|
||||
; SI-CHECK: V_MOVRELS_B32_e32
|
||||
define void @char_array(i32 addrspace(1)* %out, i32 %index) {
|
||||
entry:
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
; SMRD load with an immediate offset.
|
||||
; CHECK-LABEL: @smrd0
|
||||
; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 1 ; encoding: [0x01
|
||||
; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
|
||||
define void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(2)* %ptr, i64 1
|
||||
@ -13,7 +13,7 @@ entry:
|
||||
|
||||
; SMRD load with the largest possible immediate offset.
|
||||
; CHECK-LABEL: @smrd1
|
||||
; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 255 ; encoding: [0xff
|
||||
; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
|
||||
define void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
|
||||
entry:
|
||||
%0 = getelementptr i32 addrspace(2)* %ptr, i64 255
|
||||
@ -24,7 +24,7 @@ entry:
|
||||
|
||||
; SMRD load with an offset greater than the largest possible immediate.
|
||||
; CHECK-LABEL: @smrd2
|
||||
; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 1024
|
||||
; CHECK: S_MOV_B32 s[[OFFSET:[0-9]]], 0x400
|
||||
; CHECK: S_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
|
||||
define void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
|
||||
entry:
|
||||
@ -36,7 +36,7 @@ entry:
|
||||
|
||||
; SMRD load using the load.const intrinsic with an immediate offset
|
||||
; CHECK-LABEL: @smrd_load_const0
|
||||
; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 4 ; encoding: [0x04
|
||||
; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
|
||||
define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
main_body:
|
||||
%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
|
||||
@ -49,7 +49,7 @@ main_body:
|
||||
; SMRD load using the load.const intrinsic with an offset greater largest possible
|
||||
; immediate offset.
|
||||
; CHECK-LABEL: @smrd_load_const1
|
||||
; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 255 ; encoding: [0xff
|
||||
; CHECK: S_BUFFER_LOAD_DWORD s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
|
||||
define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
main_body:
|
||||
%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
|
||||
define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
|
||||
; SI-LABEL: @trunc_i64_to_i32_store
|
||||
; SI: S_LOAD_DWORD s0, s[0:1], 11
|
||||
; SI: S_LOAD_DWORD s0, s[0:1], 0xb
|
||||
; SI: V_MOV_B32_e32 v0, s0
|
||||
; SI: BUFFER_STORE_DWORD v0
|
||||
|
||||
|
||||
@ -19,7 +19,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[0].Y
|
||||
; SI-CHECK: @ngroups_y
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 1
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x1
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @ngroups_y (i32 addrspace(1)* %out) {
|
||||
@ -33,7 +33,7 @@ entry:
|
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; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[0].Z
|
||||
; SI-CHECK: @ngroups_z
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 2
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x2
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @ngroups_z (i32 addrspace(1)* %out) {
|
||||
@ -47,7 +47,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[0].W
|
||||
; SI-CHECK: @global_size_x
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 3
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x3
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @global_size_x (i32 addrspace(1)* %out) {
|
||||
@ -61,7 +61,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[1].X
|
||||
; SI-CHECK: @global_size_y
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 4
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x4
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @global_size_y (i32 addrspace(1)* %out) {
|
||||
@ -75,7 +75,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[1].Y
|
||||
; SI-CHECK: @global_size_z
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 5
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x5
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @global_size_z (i32 addrspace(1)* %out) {
|
||||
@ -89,7 +89,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[1].Z
|
||||
; SI-CHECK: @local_size_x
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 6
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x6
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @local_size_x (i32 addrspace(1)* %out) {
|
||||
@ -103,7 +103,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[1].W
|
||||
; SI-CHECK: @local_size_y
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 7
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x7
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @local_size_y (i32 addrspace(1)* %out) {
|
||||
@ -117,7 +117,7 @@ entry:
|
||||
; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; R600-CHECK: MOV [[VAL]], KC0[2].X
|
||||
; SI-CHECK: @local_size_z
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 8
|
||||
; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0x8
|
||||
; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
|
||||
; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
|
||||
define void @local_size_z (i32 addrspace(1)* %out) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user