mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-10 02:29:32 +00:00
To allow the X86 verbose assembly to print its informative comments
when used with symbolic disassembly, add a check that the operand is an immediate and has not been symbolicated to MCExpr operand. I’m trying to enable the ‘C’ disassembly API option LLVMDisassembler_Option_SetInstrComments for darwin’s otool(1) that uses the llvm disassembler API. The problem is that the disassembler API can change an immediate operand to an MCExpr operand if it symbolicates it with the call backs. And if it does the code in llvm::EmitAnyX86InstComments() will crash when it assumes these operands are immediates. The fix for this is very straight forward to just protect the call to getImm() with a check of isImm(). So if the immediate for an instruction is symbolicated it simply doesn’t get the X86 verbose assembly comments: % otool -tV test_asm.o test_asm.o: (__TEXT,__text) section _t1: 0000000000000000 vpshufd $_t1, %xmm1, %xmm0 0000000000000005 retq 0000000000000006 nopw %cs:_t1(%rax,%rax) _t2: 0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3] 0000000000000015 retq 0000000000000016 nopw %cs:_t1(%rax,%rax) _t3: 0000000000000020 vpshufd $_t1, %xmm1, %xmm0 0000000000000025 retq 0000000000000026 nopw %cs:_t1(%rax,%rax) _t4: 0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0] 0000000000000035 retq The fact that the immediate $0x0 is being symbolicated at all in this case is a different problem which my next patch will address. rdar://10989286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199697 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby
parent
07b072b24d
commit
bf2712ae43
@ -38,6 +38,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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DestName = getRegName(MI->getOperand(0).getReg());
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Src1Name = getRegName(MI->getOperand(1).getReg());
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Src2Name = getRegName(MI->getOperand(2).getReg());
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if(MI->getOperand(3).isImm())
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DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
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break;
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@ -65,6 +66,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::VPALIGNR128rm:
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Src2Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePALIGNRMask(MVT::v16i8,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -75,6 +77,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::VPALIGNR256rm:
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Src2Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePALIGNRMask(MVT::v32i8,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -87,7 +90,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::PSHUFDmi:
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case X86::VPSHUFDmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePSHUFMask(MVT::v4i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFMask(MVT::v4i32,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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break;
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case X86::VPSHUFDYri:
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@ -95,7 +100,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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// FALL THROUGH.
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case X86::VPSHUFDYmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodePSHUFMask(MVT::v8i32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFMask(MVT::v8i32,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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break;
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@ -107,6 +114,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::PSHUFHWmi:
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case X86::VPSHUFHWmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFHWMask(MVT::v8i16,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -116,6 +124,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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// FALL THROUGH.
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case X86::VPSHUFHWYmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFHWMask(MVT::v16i16,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -127,6 +136,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::PSHUFLWmi:
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case X86::VPSHUFLWmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFLWMask(MVT::v8i16,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -136,6 +146,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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// FALL THROUGH.
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case X86::VPSHUFLWYmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFLWMask(MVT::v16i16,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -293,7 +304,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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// FALL THROUGH.
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case X86::SHUFPDrmi:
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case X86::VSHUFPDrmi:
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DecodeSHUFPMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodeSHUFPMask(MVT::v2f64,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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@ -302,7 +315,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VSHUFPDYrmi:
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DecodeSHUFPMask(MVT::v4f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodeSHUFPMask(MVT::v4f64,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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@ -314,7 +329,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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// FALL THROUGH.
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case X86::SHUFPSrmi:
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case X86::VSHUFPSrmi:
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DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodeSHUFPMask(MVT::v4f32,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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@ -323,7 +340,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VSHUFPSYrmi:
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DecodeSHUFPMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodeSHUFPMask(MVT::v8f32,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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@ -405,7 +424,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPSmi:
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DecodePSHUFMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFMask(MVT::v4f32,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -413,7 +434,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPSYmi:
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DecodePSHUFMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFMask(MVT::v8f32,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -421,7 +444,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPDmi:
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DecodePSHUFMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFMask(MVT::v2f64,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -429,7 +454,9 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPDYmi:
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DecodePSHUFMask(MVT::v4f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodePSHUFMask(MVT::v4f64,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -440,6 +467,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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case X86::VPERM2F128rm:
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case X86::VPERM2I128rm:
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// For instruction comments purpose, assume the 256-bit vector is v4i64.
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodeVPERM2X128Mask(MVT::v4i64,
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MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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@ -452,6 +480,7 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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// FALL THROUGH.
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case X86::VPERMQYmi:
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case X86::VPERMPDYmi:
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if(MI->getOperand(MI->getNumOperands()-1).isImm())
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DecodeVPERMMask(MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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