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fixed incorrect lowering of ISD::SUB node. SUB has only one result value.
It wasn't caught during tests because we never got a sub generated, (i8 was always getting promoted to int, which in turn was broken into subc/sube). Though the optimizer leaves an i8 sub now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77178 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1573,11 +1573,20 @@ SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
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SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl);
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SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag);
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if (Op.getOpcode() == ISD::SUBE)
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return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
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Op.getOperand(2));
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else
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return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
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switch (Op.getOpcode()) {
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case ISD::SUBE:
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return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1),
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Op.getOperand(2));
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break;
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case ISD::SUBC:
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return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1));
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break;
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case ISD::SUB:
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return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1));
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break;
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default:
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assert (0 && "Opcode unknown.");
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}
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}
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void PIC16TargetLowering::InitReservedFrameCount(const Function *F) {
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