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ARM two-operand forms for vhadd and vhsub instructions.
rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6986,6 +6986,68 @@ def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
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def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
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(VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
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// Two-operand variants for VHSUB.
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// Signed.
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def : NEONInstAlias<"vhsub${p}.s8 $Vdn, $Vm",
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(VHSUBsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.s16 $Vdn, $Vm",
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(VHSUBsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.s32 $Vdn, $Vm",
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(VHSUBsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.s8 $Vdn, $Vm",
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(VHSUBsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.s16 $Vdn, $Vm",
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(VHSUBsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.s32 $Vdn, $Vm",
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(VHSUBsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// Unsigned.
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def : NEONInstAlias<"vhsub${p}.u8 $Vdn, $Vm",
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(VHSUBuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.u16 $Vdn, $Vm",
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(VHSUBuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.u32 $Vdn, $Vm",
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(VHSUBuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.u8 $Vdn, $Vm",
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(VHSUBuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.u16 $Vdn, $Vm",
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(VHSUBuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhsub${p}.u32 $Vdn, $Vm",
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(VHSUBuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// Two-operand variants for VHADD.
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// Signed.
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def : NEONInstAlias<"vhadd${p}.s8 $Vdn, $Vm",
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(VHADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.s16 $Vdn, $Vm",
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(VHADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.s32 $Vdn, $Vm",
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(VHADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.s8 $Vdn, $Vm",
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(VHADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.s16 $Vdn, $Vm",
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(VHADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.s32 $Vdn, $Vm",
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(VHADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// Unsigned.
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def : NEONInstAlias<"vhadd${p}.u8 $Vdn, $Vm",
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(VHADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.u16 $Vdn, $Vm",
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(VHADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.u32 $Vdn, $Vm",
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(VHADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.u8 $Vdn, $Vm",
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(VHADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.u16 $Vdn, $Vm",
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(VHADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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def : NEONInstAlias<"vhadd${p}.u32 $Vdn, $Vm",
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(VHADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
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// Two-operand variants for VRHADD.
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// Signed.
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@ -65,6 +65,33 @@
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@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3]
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vhadd.u32 q8, q8, q9
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vhadd.s8 d11, d24
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vhadd.s16 d12, d23
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vhadd.s32 d13, d22
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vhadd.u8 d14, d21
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vhadd.u16 d15, d20
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vhadd.u32 d16, d19
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vhadd.s8 q1, q12
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vhadd.s16 q2, q11
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vhadd.s32 q3, q10
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vhadd.u8 q4, q9
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vhadd.u16 q5, q8
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vhadd.u32 q6, q7
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@ CHECK: vhadd.s8 d11, d11, d24 @ encoding: [0x28,0xb0,0x0b,0xf2]
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@ CHECK: vhadd.s16 d12, d12, d23 @ encoding: [0x27,0xc0,0x1c,0xf2]
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@ CHECK: vhadd.s32 d13, d13, d22 @ encoding: [0x26,0xd0,0x2d,0xf2]
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@ CHECK: vhadd.u8 d14, d14, d21 @ encoding: [0x25,0xe0,0x0e,0xf3]
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@ CHECK: vhadd.u16 d15, d15, d20 @ encoding: [0x24,0xf0,0x1f,0xf3]
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@ CHECK: vhadd.u32 d16, d16, d19 @ encoding: [0xa3,0x00,0x60,0xf3]
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@ CHECK: vhadd.s8 q1, q1, q12 @ encoding: [0x68,0x20,0x02,0xf2]
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@ CHECK: vhadd.s16 q2, q2, q11 @ encoding: [0x66,0x40,0x14,0xf2]
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@ CHECK: vhadd.s32 q3, q3, q10 @ encoding: [0x64,0x60,0x26,0xf2]
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@ CHECK: vhadd.u8 q4, q4, q9 @ encoding: [0x62,0x80,0x08,0xf3]
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@ CHECK: vhadd.u16 q5, q5, q8 @ encoding: [0x60,0xa0,0x1a,0xf3]
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@ CHECK: vhadd.u32 q6, q6, q7 @ encoding: [0x4e,0xc0,0x2c,0xf3]
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vrhadd.s8 d16, d16, d17
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vrhadd.s16 d16, d16, d17
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vrhadd.s32 d16, d16, d17
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@ -132,3 +132,29 @@
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vrsubhn.i32 d16, q8, q9
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@ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
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vrsubhn.i64 d16, q8, q9
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vhsub.s8 d11, d24
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vhsub.s16 d12, d23
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vhsub.s32 d13, d22
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vhsub.u8 d14, d21
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vhsub.u16 d15, d20
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vhsub.u32 d16, d19
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vhsub.s8 q1, q12
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vhsub.s16 q2, q11
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vhsub.s32 q3, q10
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vhsub.u8 q4, q9
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vhsub.u16 q5, q8
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vhsub.u32 q6, q7
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@ CHECK: vhsub.s8 d11, d11, d24 @ encoding: [0x28,0xb2,0x0b,0xf2]
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@ CHECK: vhsub.s16 d12, d12, d23 @ encoding: [0x27,0xc2,0x1c,0xf2]
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@ CHECK: vhsub.s32 d13, d13, d22 @ encoding: [0x26,0xd2,0x2d,0xf2]
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@ CHECK: vhsub.u8 d14, d14, d21 @ encoding: [0x25,0xe2,0x0e,0xf3]
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@ CHECK: vhsub.u16 d15, d15, d20 @ encoding: [0x24,0xf2,0x1f,0xf3]
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@ CHECK: vhsub.u32 d16, d16, d19 @ encoding: [0xa3,0x02,0x60,0xf3]
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@ CHECK: vhsub.s8 q1, q1, q12 @ encoding: [0x68,0x22,0x02,0xf2]
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@ CHECK: vhsub.s16 q2, q2, q11 @ encoding: [0x66,0x42,0x14,0xf2]
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@ CHECK: vhsub.s32 q3, q3, q10 @ encoding: [0x64,0x62,0x26,0xf2]
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@ CHECK: vhsub.u8 q4, q4, q9 @ encoding: [0x62,0x82,0x08,0xf3]
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@ CHECK: vhsub.u16 q5, q5, q8 @ encoding: [0x60,0xa2,0x1a,0xf3]
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@ CHECK: vhsub.u32 q6, q6, q7 @ encoding: [0x4e,0xc2,0x2c,0xf3]
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