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ARM two-operand forms for vhadd and vhsub instructions.

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rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-04-16 23:00:25 +00:00
parent f23293793a
commit bf42f24e6e
3 changed files with 115 additions and 0 deletions
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62
lib/Target/ARM/ARMInstrNEON.td
View File

@ -6986,6 +6986,68 @@ def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
(VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
// Two-operand variants for VHSUB.
// Signed.
def : NEONInstAlias<"vhsub${p}.s8 $Vdn, $Vm",
(VHSUBsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.s16 $Vdn, $Vm",
(VHSUBsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.s32 $Vdn, $Vm",
(VHSUBsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.s8 $Vdn, $Vm",
(VHSUBsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.s16 $Vdn, $Vm",
(VHSUBsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.s32 $Vdn, $Vm",
(VHSUBsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
// Unsigned.
def : NEONInstAlias<"vhsub${p}.u8 $Vdn, $Vm",
(VHSUBuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.u16 $Vdn, $Vm",
(VHSUBuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.u32 $Vdn, $Vm",
(VHSUBuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.u8 $Vdn, $Vm",
(VHSUBuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.u16 $Vdn, $Vm",
(VHSUBuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhsub${p}.u32 $Vdn, $Vm",
(VHSUBuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
// Two-operand variants for VHADD.
// Signed.
def : NEONInstAlias<"vhadd${p}.s8 $Vdn, $Vm",
(VHADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.s16 $Vdn, $Vm",
(VHADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.s32 $Vdn, $Vm",
(VHADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.s8 $Vdn, $Vm",
(VHADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.s16 $Vdn, $Vm",
(VHADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.s32 $Vdn, $Vm",
(VHADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
// Unsigned.
def : NEONInstAlias<"vhadd${p}.u8 $Vdn, $Vm",
(VHADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.u16 $Vdn, $Vm",
(VHADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.u32 $Vdn, $Vm",
(VHADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.u8 $Vdn, $Vm",
(VHADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.u16 $Vdn, $Vm",
(VHADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
def : NEONInstAlias<"vhadd${p}.u32 $Vdn, $Vm",
(VHADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
// Two-operand variants for VRHADD.
// Signed.

27
test/MC/ARM/neon-add-encoding.s
View File

@ -65,6 +65,33 @@
@ CHECK: vhadd.u32 q8, q8, q9 @ encoding: [0xe2,0x00,0x60,0xf3]
vhadd.u32 q8, q8, q9
vhadd.s8 d11, d24
vhadd.s16 d12, d23
vhadd.s32 d13, d22
vhadd.u8 d14, d21
vhadd.u16 d15, d20
vhadd.u32 d16, d19
vhadd.s8 q1, q12
vhadd.s16 q2, q11
vhadd.s32 q3, q10
vhadd.u8 q4, q9
vhadd.u16 q5, q8
vhadd.u32 q6, q7
@ CHECK: vhadd.s8 d11, d11, d24 @ encoding: [0x28,0xb0,0x0b,0xf2]
@ CHECK: vhadd.s16 d12, d12, d23 @ encoding: [0x27,0xc0,0x1c,0xf2]
@ CHECK: vhadd.s32 d13, d13, d22 @ encoding: [0x26,0xd0,0x2d,0xf2]
@ CHECK: vhadd.u8 d14, d14, d21 @ encoding: [0x25,0xe0,0x0e,0xf3]
@ CHECK: vhadd.u16 d15, d15, d20 @ encoding: [0x24,0xf0,0x1f,0xf3]
@ CHECK: vhadd.u32 d16, d16, d19 @ encoding: [0xa3,0x00,0x60,0xf3]
@ CHECK: vhadd.s8 q1, q1, q12 @ encoding: [0x68,0x20,0x02,0xf2]
@ CHECK: vhadd.s16 q2, q2, q11 @ encoding: [0x66,0x40,0x14,0xf2]
@ CHECK: vhadd.s32 q3, q3, q10 @ encoding: [0x64,0x60,0x26,0xf2]
@ CHECK: vhadd.u8 q4, q4, q9 @ encoding: [0x62,0x80,0x08,0xf3]
@ CHECK: vhadd.u16 q5, q5, q8 @ encoding: [0x60,0xa0,0x1a,0xf3]
@ CHECK: vhadd.u32 q6, q6, q7 @ encoding: [0x4e,0xc0,0x2c,0xf3]
vrhadd.s8 d16, d16, d17
vrhadd.s16 d16, d16, d17
vrhadd.s32 d16, d16, d17

26
test/MC/ARM/neon-sub-encoding.s
View File

@ -132,3 +132,29 @@
vrsubhn.i32 d16, q8, q9
@ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
vrsubhn.i64 d16, q8, q9
vhsub.s8 d11, d24
vhsub.s16 d12, d23
vhsub.s32 d13, d22
vhsub.u8 d14, d21
vhsub.u16 d15, d20
vhsub.u32 d16, d19
vhsub.s8 q1, q12
vhsub.s16 q2, q11
vhsub.s32 q3, q10
vhsub.u8 q4, q9
vhsub.u16 q5, q8
vhsub.u32 q6, q7
@ CHECK: vhsub.s8 d11, d11, d24 @ encoding: [0x28,0xb2,0x0b,0xf2]
@ CHECK: vhsub.s16 d12, d12, d23 @ encoding: [0x27,0xc2,0x1c,0xf2]
@ CHECK: vhsub.s32 d13, d13, d22 @ encoding: [0x26,0xd2,0x2d,0xf2]
@ CHECK: vhsub.u8 d14, d14, d21 @ encoding: [0x25,0xe2,0x0e,0xf3]
@ CHECK: vhsub.u16 d15, d15, d20 @ encoding: [0x24,0xf2,0x1f,0xf3]
@ CHECK: vhsub.u32 d16, d16, d19 @ encoding: [0xa3,0x02,0x60,0xf3]
@ CHECK: vhsub.s8 q1, q1, q12 @ encoding: [0x68,0x22,0x02,0xf2]
@ CHECK: vhsub.s16 q2, q2, q11 @ encoding: [0x66,0x42,0x14,0xf2]
@ CHECK: vhsub.s32 q3, q3, q10 @ encoding: [0x64,0x62,0x26,0xf2]
@ CHECK: vhsub.u8 q4, q4, q9 @ encoding: [0x62,0x82,0x08,0xf3]
@ CHECK: vhsub.u16 q5, q5, q8 @ encoding: [0x60,0xa2,0x1a,0xf3]
@ CHECK: vhsub.u32 q6, q6, q7 @ encoding: [0x4e,0xc2,0x2c,0xf3]