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Add a subtarget feature for the stfiwx instruction. I know the G5 has it,

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but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-28 07:08:22 +00:00
parent c7d855ea2e
commit bf751e2d6f
2 changed files with 6 additions and 2 deletions
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6
lib/Target/PowerPC/PPC.td
View File

@ -29,6 +29,8 @@ def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
"Enable GPUL instructions">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
"Enable the fsqrt instruction">;
def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
"Enable the stfiwx instruction">;
//===----------------------------------------------------------------------===//
// Register File Description
@ -58,10 +60,10 @@ def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"g5", G5Itineraries,
[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;

2
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -37,6 +37,7 @@ protected:
bool Has64BitRegs;
bool HasAltivec;
bool HasFSQRT;
bool HasSTFIWX;
bool IsAIX;
bool IsDarwin;
public:
@ -60,6 +61,7 @@ public:
bool hasFSQRT() const { return HasFSQRT; }
bool hasSTFIWX() const { return HasSTFIWX; }
bool has64BitRegs() const { return Has64BitRegs; }
bool hasAltivec() const { return HasAltivec; }