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MachineInstr::isPredicable() is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37599 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -447,7 +447,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
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if (TID->Flags & M_CLOBBERS_PRED)
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BBI.ClobbersPred = true;
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if (!I->isPredicable()) {
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if ((TID->Flags & M_PREDICABLE) == 0) {
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BBI.IsUnpredicable = true;
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return;
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}
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@ -881,7 +881,8 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI) {
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while (TT != BBI.TrueBB->end() && FT != BBI.FalseBB->end()) {
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if (TT->isIdenticalTo(FT))
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Dups.push_back(TT); // Will erase these later.
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else if (!TT->isPredicable() && !FT->isPredicable())
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else if ((TT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0 ||
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(FT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0)
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return false; // Can't if-convert. Abort!
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++TT;
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++FT;
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@ -890,15 +891,13 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI) {
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// One of the two pathes have more terminators, make sure they are
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// all predicable.
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while (TT != BBI.TrueBB->end()) {
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if (!TT->isPredicable()) {
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if ((TT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0)
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return false; // Can't if-convert. Abort!
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}
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++TT;
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}
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while (FT != BBI.FalseBB->end()) {
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if (!FT->isPredicable()) {
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if ((FT->getInstrDescriptor()->Flags & M_PREDICABLE) == 0)
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return false; // Can't if-convert. Abort!
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}
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++FT;
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}
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}
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@ -184,10 +184,6 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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}
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}
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bool MachineInstr::isPredicable() const {
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return TID->Flags & M_PREDICABLE;
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}
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/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
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/// the specific register or -1 if it is not found. It further tightening
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/// the search criteria to a use that kills the register if isKill is true.
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