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Define multiclasses for FP-to-FP instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-08 03:29:22 +00:00
parent a8de1c1be0
commit bfca0798cf
1 changed files with 11 additions and 11 deletions
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22
lib/Target/Mips/MipsInstrFPU.td
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@ -89,11 +89,13 @@ multiclass FFR1_L_M<bits<6> funct, string opstr> {
def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
} }
multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp> // FP-to-FP conversion instructions.
{ multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
def _S32 : FFR1P<funct, 16, asmstr, "s", FGR32, FGR32, FOp>; def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
def _D32 : FFR1P<funct, 17, asmstr, "d", AFGR64, AFGR64, FOp>, def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
Requires<[NotFP64bit]>; Requires<[NotFP64bit]>;
def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
Requires<[IsFP64bit]>;
} }
multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> { multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
@ -141,11 +143,9 @@ let Predicates = [IsFP64bit] in {
def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>; def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
} }
let ft = 0 in { defm FABS : FFR1P_M<0x5, "abs", fabs>;
defm FABS : FFR1_2<0b000101, "abs", fabs>; defm FNEG : FFR1P_M<0x7, "neg", fneg>;
defm FNEG : FFR1_2<0b000111, "neg", fneg>; defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>;
defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
}
// The odd-numbered registers are only referenced when doing loads, // The odd-numbered registers are only referenced when doing loads,
// stores, and moves between floating-point and integer registers. // stores, and moves between floating-point and integer registers.
@ -333,7 +333,7 @@ def fpimm0neg : PatLeaf<(fpimm), [{
}]>; }]>;
def : Pat<(f32 fpimm0), (MTC1 ZERO)>; def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>; def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>; def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;