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Change mips16 delay slot jumps to non delay slot forms by default.

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We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166990 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2012-10-30 00:54:49 +00:00
parent 803ea1c40a
commit c09856b535
4 changed files with 13 additions and 6 deletions
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2
lib/Target/Mips/Mips16InstrInfo.cpp
View File

@ -126,7 +126,7 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
default:
return false;
case Mips::RetRA16:
ExpandRetRA16(MBB, MI, Mips::JrRa16);
ExpandRetRA16(MBB, MI, Mips::JrcRa16);
break;
}

11
lib/Target/Mips/Mips16InstrInfo.td
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@ -515,6 +515,13 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
let isBarrier=1;
}
def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> {
let isBranch = 1;
let isIndirectBranch = 1;
let isTerminator=1;
let isBarrier=1;
}
def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
let isBranch = 1;
let isIndirectBranch = 1;
@ -1011,10 +1018,10 @@ def: Mips16Pat<
// Jump and Link (Call)
let isCall=1, hasDelaySlot=1 in
let isCall=1, hasDelaySlot=0 in
def JumpLinkReg16:
FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
"jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
// Mips16 pseudos
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,

4
test/CodeGen/Mips/helloworld.ll
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@ -24,10 +24,10 @@ entry:
; C1: addiu ${{[0-9]+}}, %lo($.str)
; C2: move $25, ${{[0-9]+}}
; C1: move $gp, ${{[0-9]+}}
; C1: jalr ${{[0-9]+}}
; C1: jalrc ${{[0-9]+}}
; SR: restore $ra, [[FS]]
; PE: li $2, 0
; PE: jr $ra
; PE: jrc $ra
}

2
test/CodeGen/Mips/null.ll
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@ -8,6 +8,6 @@ entry:
; 16: .set mips16 # @main
; 16: jr $ra
; 16: jrc $ra
}