6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-01 10:57:21 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Add comment and simplify function.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187371 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-07-29 19:08:34 +00:00
parent 1aaa5cbab9
commit c0fa31d51b
1 changed files with 14 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
View File

@ -230,35 +230,26 @@ bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
switch (MI.getOpcode()) {
case Mips::BEQ:
if (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS))
return true;
break;
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
case Mips::BEQ64:
if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS))
return true;
break;
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
case Mips::BNE:
if (isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
return true;
break;
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
case Mips::BNE64:
if (isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS))
return true;
break;
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
case Mips::BC1T:
if (isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS))
return true;
break;
// bc1t $fcc0, $L1 => bc1t $L1
return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
case Mips::BC1F:
if (isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS))
return true;
break;
// bc1f $fcc0, $L1 => bc1f $L1
return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
case Mips::OR:
if (isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS))
return true;
break;
// or $r0, $r1, $zero => move $r0, $r1
return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
default: return false;
}
return false;
}