mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
3480d1b84e
commit
c149fbbe27
@ -447,6 +447,9 @@ def int_mips_addvi_w : GCCBuiltin<"__builtin_msa_addvi_w">,
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def int_mips_addvi_d : GCCBuiltin<"__builtin_msa_addvi_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [Commutative]>;
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def int_mips_and_v : GCCBuiltin<"__builtin_msa_and_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_andi_b : GCCBuiltin<"__builtin_msa_andi_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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@ -558,9 +561,15 @@ def int_mips_binsri_w : GCCBuiltin<"__builtin_msa_binsri_w">,
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def int_mips_binsri_d : GCCBuiltin<"__builtin_msa_binsri_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], []>;
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def int_mips_bmnz_v : GCCBuiltin<"__builtin_msa_bmnz_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_bmnzi_b : GCCBuiltin<"__builtin_msa_bmnzi_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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def int_mips_bmz_v : GCCBuiltin<"__builtin_msa_bmz_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_bmzi_b : GCCBuiltin<"__builtin_msa_bmzi_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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@ -582,6 +591,9 @@ def int_mips_bnegi_w : GCCBuiltin<"__builtin_msa_bnegi_w">,
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def int_mips_bnegi_d : GCCBuiltin<"__builtin_msa_bnegi_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], []>;
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def int_mips_bsel_v : GCCBuiltin<"__builtin_msa_bsel_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_bseli_b : GCCBuiltin<"__builtin_msa_bseli_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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def int_mips_bseli_h : GCCBuiltin<"__builtin_msa_bseli_h">,
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@ -1219,9 +1231,15 @@ def int_mips_nlzc_w : GCCBuiltin<"__builtin_msa_nlzc_w">,
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def int_mips_nlzc_d : GCCBuiltin<"__builtin_msa_nlzc_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], []>;
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def int_mips_nor_v : GCCBuiltin<"__builtin_msa_nor_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_nori_b : GCCBuiltin<"__builtin_msa_nori_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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def int_mips_or_v : GCCBuiltin<"__builtin_msa_or_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_ori_b : GCCBuiltin<"__builtin_msa_ori_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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@ -1430,6 +1448,9 @@ def int_mips_vshf_w : GCCBuiltin<"__builtin_msa_vshf_w">,
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def int_mips_vshf_d : GCCBuiltin<"__builtin_msa_vshf_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [Commutative]>;
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def int_mips_xor_v : GCCBuiltin<"__builtin_msa_xor_v">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>;
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def int_mips_xori_b : GCCBuiltin<"__builtin_msa_xori_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>;
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}
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@ -109,3 +109,8 @@ class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{22-21} = df;
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let Inst{5-0} = minor;
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}
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class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
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let Inst{25-21} = major;
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let Inst{5-0} = minor;
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}
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@ -65,6 +65,8 @@ class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
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class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
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class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
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class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
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class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
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class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
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@ -127,8 +129,12 @@ class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
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class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
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class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
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class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
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class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
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class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
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class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
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class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
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@ -141,6 +147,8 @@ class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
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class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
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class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
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class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
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class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
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class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
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@ -508,8 +516,12 @@ class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
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class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
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class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
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class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
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class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
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class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
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class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
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class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
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@ -631,6 +643,8 @@ class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
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class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
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class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
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class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
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class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
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// Instruction desc.
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@ -784,6 +798,16 @@ class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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string Constraints = "$wd = $wd_in";
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}
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class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass itin, RegisterClass RCWD,
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RegisterClass RCWS, RegisterClass RCWT = RCWS> {
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dag OutOperandList = (outs RCWD:$wd);
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dag InOperandList = (ins RCWS:$ws, RCWT:$wt);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
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list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, RCWT:$wt))];
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InstrItinClass Itinerary = itin;
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}
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class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, NoItinerary,
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MSA128, MSA128>, IsCommutable;
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class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, NoItinerary,
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@ -850,6 +874,9 @@ class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", int_mips_addvi_w, NoItinerary,
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class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", int_mips_addvi_d, NoItinerary,
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MSA128, MSA128>;
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class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", int_mips_and_v, NoItinerary,
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MSA128, MSA128>;
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class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", int_mips_andi_b, NoItinerary,
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MSA128, MSA128>;
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@ -969,9 +996,15 @@ class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w,
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class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d,
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NoItinerary, MSA128, MSA128>;
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class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, NoItinerary,
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MSA128, MSA128>;
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class BMNZI_B_DESC : MSA_I8_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b, NoItinerary,
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MSA128, MSA128>;
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class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, NoItinerary,
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MSA128, MSA128>;
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class BMZI_B_DESC : MSA_I8_DESC_BASE<"bmzi.b", int_mips_bmzi_b, NoItinerary,
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MSA128, MSA128>;
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@ -993,6 +1026,9 @@ class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w,
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class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d,
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NoItinerary, MSA128, MSA128>;
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class BSEL_V_DESC : MSA_VEC_DESC_BASE<"bsel.v", int_mips_bsel_v, NoItinerary,
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MSA128, MSA128>;
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class BSELI_B_DESC : MSA_I8_DESC_BASE<"bseli.b", int_mips_bseli_b, NoItinerary,
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MSA128, MSA128>;
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@ -1661,9 +1697,15 @@ class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", int_mips_nlzc_w,
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class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", int_mips_nlzc_d,
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NoItinerary, MSA128, MSA128>;
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class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", int_mips_nor_v, NoItinerary,
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MSA128, MSA128>;
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class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", int_mips_nori_b, NoItinerary,
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MSA128, MSA128>;
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class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", int_mips_or_v, NoItinerary,
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MSA128, MSA128>;
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class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", int_mips_ori_b, NoItinerary,
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MSA128, MSA128>;
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@ -1888,6 +1930,9 @@ class VSHF_W_DESC : MSA_3R_DESC_BASE<"vshf.w", int_mips_vshf_w,
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class VSHF_D_DESC : MSA_3R_DESC_BASE<"vshf.d", int_mips_vshf_d,
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NoItinerary, MSA128, MSA128>;
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class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", int_mips_xor_v, NoItinerary,
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MSA128, MSA128>;
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class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", int_mips_xori_b, NoItinerary,
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MSA128, MSA128>;
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// Instruction defs.
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@ -1921,6 +1966,8 @@ def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC, Requires<[HasMSA]>;
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def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC, Requires<[HasMSA]>;
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def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC, Requires<[HasMSA]>;
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def AND_V : AND_V_ENC, AND_V_DESC, Requires<[HasMSA]>;
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def ANDI_B : ANDI_B_ENC, ANDI_B_DESC, Requires<[HasMSA]>;
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def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC, Requires<[HasMSA]>;
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@ -1983,8 +2030,12 @@ def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC, Requires<[HasMSA]>;
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def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC, Requires<[HasMSA]>;
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def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC, Requires<[HasMSA]>;
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def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC, Requires<[HasMSA]>;
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def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC, Requires<[HasMSA]>;
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def BMZ_V : BMZ_V_ENC, BMZ_V_DESC, Requires<[HasMSA]>;
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def BMZI_B : BMZI_B_ENC, BMZI_B_DESC, Requires<[HasMSA]>;
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def BNEG_B : BNEG_B_ENC, BNEG_B_DESC, Requires<[HasMSA]>;
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@ -1997,6 +2048,8 @@ def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC, Requires<[HasMSA]>;
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def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC, Requires<[HasMSA]>;
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def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC, Requires<[HasMSA]>;
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def BSEL_V : BSEL_V_ENC, BSEL_V_DESC, Requires<[HasMSA]>;
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def BSELI_B : BSELI_B_ENC, BSELI_B_DESC, Requires<[HasMSA]>;
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def BSET_B : BSET_B_ENC, BSET_B_DESC, Requires<[HasMSA]>;
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@ -2363,8 +2416,12 @@ def NLZC_H : NLZC_H_ENC, NLZC_H_DESC, Requires<[HasMSA]>;
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def NLZC_W : NLZC_W_ENC, NLZC_W_DESC, Requires<[HasMSA]>;
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def NLZC_D : NLZC_D_ENC, NLZC_D_DESC, Requires<[HasMSA]>;
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def NOR_V : NOR_V_ENC, NOR_V_DESC, Requires<[HasMSA]>;
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def NORI_B : NORI_B_ENC, NORI_B_DESC, Requires<[HasMSA]>;
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def OR_V : OR_V_ENC, OR_V_DESC, Requires<[HasMSA]>;
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def ORI_B : ORI_B_ENC, ORI_B_DESC, Requires<[HasMSA]>;
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def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC, Requires<[HasMSA]>;
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@ -2486,6 +2543,8 @@ def VSHF_H : VSHF_H_ENC, VSHF_H_DESC, Requires<[HasMSA]>;
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def VSHF_W : VSHF_W_ENC, VSHF_W_DESC, Requires<[HasMSA]>;
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def VSHF_D : VSHF_D_ENC, VSHF_D_DESC, Requires<[HasMSA]>;
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def XOR_V : XOR_V_ENC, XOR_V_DESC, Requires<[HasMSA]>;
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def XORI_B : XORI_B_ENC, XORI_B_DESC, Requires<[HasMSA]>;
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// Patterns.
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176
test/CodeGen/Mips/msa/vec.ll
Normal file
176
test/CodeGen/Mips/msa/vec.ll
Normal file
@ -0,0 +1,176 @@
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; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
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;
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; Test the MSA intrinsics that are encoded with the VEC instruction format.
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@llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_and_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_and_v_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_and_v_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_and_v_b_ARG2
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%2 = bitcast <16 x i8> %0 to <16 x i8>
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%3 = bitcast <16 x i8> %1 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.mips.and.v(<16 x i8> %2, <16 x i8> %3)
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%5 = bitcast <16 x i8> %4 to <16 x i8>
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store <16 x i8> %5, <16 x i8>* @llvm_mips_and_v_b_RES
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ret void
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}
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; CHECK: llvm_mips_and_v_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
|
||||
; CHECK: and.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_and_v_b_test
|
||||
;
|
||||
@llvm_mips_bmnz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_bmnz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_bmnz_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_bmnz_v_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_bmnz_v_b_ARG2
|
||||
%2 = bitcast <16 x i8> %0 to <16 x i8>
|
||||
%3 = bitcast <16 x i8> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.bmnz.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <16 x i8>
|
||||
store <16 x i8> %5, <16 x i8>* @llvm_mips_bmnz_v_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_bmnz_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: bmnz.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_bmnz_v_b_test
|
||||
;
|
||||
@llvm_mips_bmz_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_bmz_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_bmz_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_bmz_v_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_bmz_v_b_ARG2
|
||||
%2 = bitcast <16 x i8> %0 to <16 x i8>
|
||||
%3 = bitcast <16 x i8> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.bmz.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <16 x i8>
|
||||
store <16 x i8> %5, <16 x i8>* @llvm_mips_bmz_v_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_bmz_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: bmz.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_bmz_v_b_test
|
||||
;
|
||||
@llvm_mips_bmz_v_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_bmz_v_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
||||
@llvm_mips_bmz_v_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
||||
|
||||
@llvm_mips_bsel_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_bsel_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_bsel_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_bsel_v_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_bsel_v_b_ARG2
|
||||
%2 = bitcast <16 x i8> %0 to <16 x i8>
|
||||
%3 = bitcast <16 x i8> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.bsel.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <16 x i8>
|
||||
store <16 x i8> %5, <16 x i8>* @llvm_mips_bsel_v_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_bsel_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: bsel.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_bsel_v_b_test
|
||||
;
|
||||
@llvm_mips_nor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_nor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_nor_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_nor_v_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_nor_v_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_nor_v_b_ARG2
|
||||
%2 = bitcast <16 x i8> %0 to <16 x i8>
|
||||
%3 = bitcast <16 x i8> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.nor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <16 x i8>
|
||||
store <16 x i8> %5, <16 x i8>* @llvm_mips_nor_v_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_nor_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: nor.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_nor_v_b_test
|
||||
;
|
||||
@llvm_mips_or_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_or_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_or_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_or_v_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_or_v_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_or_v_b_ARG2
|
||||
%2 = bitcast <16 x i8> %0 to <16 x i8>
|
||||
%3 = bitcast <16 x i8> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.or.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <16 x i8>
|
||||
store <16 x i8> %5, <16 x i8>* @llvm_mips_or_v_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_or_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: or.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_or_v_b_test
|
||||
;
|
||||
@llvm_mips_xor_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_xor_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_xor_v_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_xor_v_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_xor_v_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_xor_v_b_ARG2
|
||||
%2 = bitcast <16 x i8> %0 to <16 x i8>
|
||||
%3 = bitcast <16 x i8> %1 to <16 x i8>
|
||||
%4 = tail call <16 x i8> @llvm.mips.xor.v(<16 x i8> %2, <16 x i8> %3)
|
||||
%5 = bitcast <16 x i8> %4 to <16 x i8>
|
||||
store <16 x i8> %5, <16 x i8>* @llvm_mips_xor_v_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: llvm_mips_xor_v_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: xor.v
|
||||
; CHECK: st.b
|
||||
; CHECK: .size llvm_mips_xor_v_b_test
|
||||
;
|
||||
declare <16 x i8> @llvm.mips.and.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.bmnz.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.bmz.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.bsel.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.nor.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.or.v(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.xor.v(<16 x i8>, <16 x i8>) nounwind
|
||||
Loading…
Reference in New Issue
Block a user