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Fix ARM fast isel to correctly flag memory operands to stores. This fixes

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-verify-machineinstrs failures on several tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132268 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich
2011-05-28 20:34:49 +00:00
parent b6aacae941
commit c152aa6c86
1 changed files with 7 additions and 5 deletions
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12
lib/Target/ARM/ARMFastISel.cpp
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@@ -207,7 +207,8 @@ class ARMFastISel : public FastISel {
bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
void AddLoadStoreOperands(EVT VT, Address &Addr, void AddLoadStoreOperands(EVT VT, Address &Addr,
const MachineInstrBuilder &MIB); const MachineInstrBuilder &MIB,
unsigned Flags);
}; };
} // end anonymous namespace } // end anonymous namespace
@@ -852,7 +853,8 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
} }
void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr, void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
const MachineInstrBuilder &MIB) { const MachineInstrBuilder &MIB,
unsigned Flags) {
// addrmode5 output depends on the selection dag addressing dividing the // addrmode5 output depends on the selection dag addressing dividing the
// offset by 4 that it then later multiplies. Do this here as well. // offset by 4 that it then later multiplies. Do this here as well.
if (VT.getSimpleVT().SimpleTy == MVT::f32 || if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
@@ -866,7 +868,7 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
MachineMemOperand *MMO = MachineMemOperand *MMO =
FuncInfo.MF->getMachineMemOperand( FuncInfo.MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(FI, Offset), MachinePointerInfo::getFixedStack(FI, Offset),
MachineMemOperand::MOLoad, Flags,
MFI.getObjectSize(FI), MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI)); MFI.getObjectAlignment(FI));
// Now add the rest of the operands. // Now add the rest of the operands.
@@ -925,7 +927,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
ResultReg = createResultReg(RC); ResultReg = createResultReg(RC);
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg); TII.get(Opc), ResultReg);
AddLoadStoreOperands(VT, Addr, MIB); AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
return true; return true;
} }
@@ -984,7 +986,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc)) TII.get(StrOpc))
.addReg(SrcReg, getKillRegState(true)); .addReg(SrcReg, getKillRegState(true));
AddLoadStoreOperands(VT, Addr, MIB); AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
return true; return true;
} }