6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-17 21:29:20 +00:00
Code Issues Projects Releases Wiki Activity

Make scheduling class variables be 'unsigned' instead of 'int'

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-10-28 04:53:18 +00:00
parent c5ddc8b74b
commit c188b733ba
3 changed files with 6 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/Target/MachineInstrInfo.h
View File

@ -13,7 +13,6 @@
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
class MachineInstrDescriptor; class MachineInstrDescriptor;
class TmpInstruction;
class MachineInstr; class MachineInstr;
class TargetMachine; class TargetMachine;
class Value; class Value;
@ -27,7 +26,7 @@ class MachineCodeForInstruction;
typedef int MachineOpCode; typedef int MachineOpCode;
typedef int OpCodeMask; typedef int OpCodeMask;
typedef int InstrSchedClass; typedef unsigned InstrSchedClass;
const MachineOpCode INVALID_MACHINE_OPCODE = -1; const MachineOpCode INVALID_MACHINE_OPCODE = -1;

3
include/llvm/Target/TargetInstrInfo.h
View File

@ -13,7 +13,6 @@
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
class MachineInstrDescriptor; class MachineInstrDescriptor;
class TmpInstruction;
class MachineInstr; class MachineInstr;
class TargetMachine; class TargetMachine;
class Value; class Value;
@ -27,7 +26,7 @@ class MachineCodeForInstruction;
typedef int MachineOpCode; typedef int MachineOpCode;
typedef int OpCodeMask; typedef int OpCodeMask;
typedef int InstrSchedClass; typedef unsigned InstrSchedClass;
const MachineOpCode INVALID_MACHINE_OPCODE = -1; const MachineOpCode INVALID_MACHINE_OPCODE = -1;

9
include/llvm/Target/TargetSchedInfo.h
View File

@ -196,9 +196,8 @@ protected:
assert(opCode >= 0 && opCode < (int) instrRUsages.size()); assert(opCode >= 0 && opCode < (int) instrRUsages.size());
return instrRUsages[opCode]; return instrRUsages[opCode];
} }
inline const InstrClassRUsage& const InstrClassRUsage& getClassRUsage(const InstrSchedClass& sc) const {
getClassRUsage(const InstrSchedClass& sc) const { assert(sc < numSchedClasses);
assert(sc >= 0 && sc < numSchedClasses);
return classRUsages[sc]; return classRUsages[sc];
} }
@ -225,7 +224,7 @@ public:
} }
inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const { inline unsigned getMaxIssueForClass(const InstrSchedClass& sc) const {
assert(sc >= 0 && sc < numSchedClasses); assert(sc < numSchedClasses);
return classRUsages[sc].maxNumIssue; return classRUsages[sc].maxNumIssue;
} }
@ -283,7 +282,7 @@ private:
} }
protected: protected:
int numSchedClasses; unsigned numSchedClasses;
const MachineInstrInfo* mii; const MachineInstrInfo* mii;
const InstrClassRUsage* classRUsages; // raw array by sclass const InstrClassRUsage* classRUsages; // raw array by sclass
const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas] const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]