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Code Issues Projects Releases Wiki Activity

Reverting NFC changes from r218050. Instead, the warning was disabled for GCC in r218059, so these changes are no longer required.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218062 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aaron Ballman
2014-09-18 17:34:23 +00:00
parent d80c0869ee
commit c21e4e197d
12 changed files with 0 additions and 14 deletions
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1
lib/Target/AArch64/AArch64TargetMachine.h
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@@ -31,7 +31,6 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool IsLittleEndian); CodeGenOpt::Level OL, bool IsLittleEndian);
using LLVMTargetMachine::getSubtargetImpl;
const AArch64Subtarget *getSubtargetImpl() const override { const AArch64Subtarget *getSubtargetImpl() const override {
return &Subtarget; return &Subtarget;
} }

1
lib/Target/ARM/ARMTargetMachine.h
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@@ -32,7 +32,6 @@ public:
CodeGenOpt::Level OL, CodeGenOpt::Level OL,
bool isLittle); bool isLittle);
using LLVMTargetMachine::getSubtargetImpl;
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; } const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
/// \brief Register ARM analysis passes with a pass manager. /// \brief Register ARM analysis passes with a pass manager.

1
lib/Target/Hexagon/HexagonTargetMachine.h
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@@ -31,7 +31,6 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const HexagonSubtarget *getSubtargetImpl() const override { const HexagonSubtarget *getSubtargetImpl() const override {
return &Subtarget; return &Subtarget;
} }

1
lib/Target/MSP430/MSP430TargetMachine.h
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@@ -32,7 +32,6 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const MSP430Subtarget *getSubtargetImpl() const override { const MSP430Subtarget *getSubtargetImpl() const override {
return &Subtarget; return &Subtarget;
} }

1
lib/Target/Mips/MipsTargetMachine.h
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@@ -39,7 +39,6 @@ public:
void addAnalysisPasses(PassManagerBase &PM) override; void addAnalysisPasses(PassManagerBase &PM) override;
using LLVMTargetMachine::getSubtargetImpl;
const MipsSubtarget *getSubtargetImpl() const override { const MipsSubtarget *getSubtargetImpl() const override {
if (Subtarget) if (Subtarget)
return Subtarget; return Subtarget;

1
lib/Target/NVPTX/NVPTXTargetMachine.h
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@@ -35,7 +35,6 @@ public:
const TargetOptions &Options, Reloc::Model RM, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit); CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
using LLVMTargetMachine::getSubtargetImpl;
const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; } const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
ManagedStringPool *getManagedStrPool() const { ManagedStringPool *getManagedStrPool() const {

1
lib/Target/PowerPC/PPCTargetMachine.h
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@@ -32,7 +32,6 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; } const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration // Pass Pipeline Configuration

2
lib/Target/R600/AMDGPUTargetMachine.h
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@@ -33,8 +33,6 @@ public:
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine(); ~AMDGPUTargetMachine();
using LLVMTargetMachine::getSubtargetImpl;
const AMDGPUSubtarget *getSubtargetImpl() const override { const AMDGPUSubtarget *getSubtargetImpl() const override {
return &Subtarget; return &Subtarget;
} }

1
lib/Target/Sparc/SparcTargetMachine.h
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@@ -28,7 +28,6 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit); CodeGenOpt::Level OL, bool is64bit);
using LLVMTargetMachine::getSubtargetImpl;
const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration // Pass Pipeline Configuration

1
lib/Target/SystemZ/SystemZTargetMachine.h
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@@ -32,7 +32,6 @@ public:
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
// Override TargetMachine. // Override TargetMachine.
using LLVMTargetMachine::getSubtargetImpl;
const SystemZSubtarget *getSubtargetImpl() const override { const SystemZSubtarget *getSubtargetImpl() const override {
return &Subtarget; return &Subtarget;
} }

2
lib/Target/X86/X86TargetMachine.h
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@@ -31,8 +31,6 @@ public:
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; } const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
/// \brief Register X86 analysis passes with a pass manager. /// \brief Register X86 analysis passes with a pass manager.

1
lib/Target/XCore/XCoreTargetMachine.h
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@@ -27,7 +27,6 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
using LLVMTargetMachine::getSubtargetImpl;
const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; } const XCoreSubtarget *getSubtargetImpl() const override { return &Subtarget; }
// Pass Pipeline Configuration // Pass Pipeline Configuration