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split EmitNode in half to reduce indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99444 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -569,93 +569,99 @@ InstrEmitter::EmitDbgValue(SDDbgValue *sd,
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MBB->insert(InsertPos, MI);
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}
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/// EmitNode - Generate machine code for a node and needed dependencies.
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/// EmitMachineNode - Generate machine code for a target-specific node and
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/// needed dependencies.
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///
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void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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// If machine instruction
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if (Node->isMachineOpcode()) {
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unsigned Opc = Node->getMachineOpcode();
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// Handle subreg insert/extract specially
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if (Opc == TargetOpcode::EXTRACT_SUBREG ||
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Opc == TargetOpcode::INSERT_SUBREG ||
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Opc == TargetOpcode::SUBREG_TO_REG) {
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EmitSubregNode(Node, VRBaseMap);
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return;
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}
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// Handle COPY_TO_REGCLASS specially.
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if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
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EmitCopyToRegClassNode(Node, VRBaseMap);
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return;
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}
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if (Opc == TargetOpcode::IMPLICIT_DEF)
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// We want a unique VR for each IMPLICIT_DEF use.
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return;
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const TargetInstrDesc &II = TII->get(Opc);
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unsigned NumResults = CountResults(Node);
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unsigned NodeOperands = CountOperands(Node);
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bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
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II.getImplicitDefs() != 0;
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#ifndef NDEBUG
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unsigned NumMIOperands = NodeOperands + NumResults;
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assert((II.getNumOperands() == NumMIOperands ||
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HasPhysRegOuts || II.isVariadic()) &&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
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// Add result register values for things that are defined by this
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// instruction.
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if (NumResults)
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CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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bool HasOptPRefs = II.getNumDefs() > NumResults;
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assert((!HasOptPRefs || !HasPhysRegOuts) &&
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"Unable to cope with optional defs and phys regs defs!");
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unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
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for (unsigned i = NumSkip; i != NodeOperands; ++i)
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AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
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VRBaseMap);
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// Transfer all of the memory reference descriptions of this instruction.
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MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
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cast<MachineSDNode>(Node)->memoperands_end());
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if (II.usesCustomInsertionHook()) {
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// Insert this instruction into the basic block using a target
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// specific inserter which may returns a new basic block.
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MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
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InsertPos = MBB->end();
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} else {
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MBB->insert(InsertPos, MI);
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}
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// Additional results must be an physical register def.
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if (HasPhysRegOuts) {
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for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
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unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
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if (Node->hasAnyUseOfValue(i))
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EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
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// If there are no uses, mark the register as dead now, so that
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// MachineLICM/Sink can see that it's dead. Don't do this if the
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// node has a Flag value, for the benefit of targets still using
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// Flag for values in physregs.
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else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
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MI->addRegisterDead(Reg, TRI);
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}
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}
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void InstrEmitter::
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EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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unsigned Opc = Node->getMachineOpcode();
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// Handle subreg insert/extract specially
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if (Opc == TargetOpcode::EXTRACT_SUBREG ||
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Opc == TargetOpcode::INSERT_SUBREG ||
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Opc == TargetOpcode::SUBREG_TO_REG) {
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EmitSubregNode(Node, VRBaseMap);
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return;
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}
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// Handle COPY_TO_REGCLASS specially.
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if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
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EmitCopyToRegClassNode(Node, VRBaseMap);
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return;
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}
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if (Opc == TargetOpcode::IMPLICIT_DEF)
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// We want a unique VR for each IMPLICIT_DEF use.
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return;
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const TargetInstrDesc &II = TII->get(Opc);
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unsigned NumResults = CountResults(Node);
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unsigned NodeOperands = CountOperands(Node);
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bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
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II.getImplicitDefs() != 0;
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#ifndef NDEBUG
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unsigned NumMIOperands = NodeOperands + NumResults;
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assert((II.getNumOperands() == NumMIOperands ||
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HasPhysRegOuts || II.isVariadic()) &&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
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// Add result register values for things that are defined by this
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// instruction.
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if (NumResults)
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CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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bool HasOptPRefs = II.getNumDefs() > NumResults;
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assert((!HasOptPRefs || !HasPhysRegOuts) &&
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"Unable to cope with optional defs and phys regs defs!");
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unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
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for (unsigned i = NumSkip; i != NodeOperands; ++i)
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AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
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VRBaseMap);
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// Transfer all of the memory reference descriptions of this instruction.
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MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
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cast<MachineSDNode>(Node)->memoperands_end());
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if (II.usesCustomInsertionHook()) {
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// Insert this instruction into the basic block using a target
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// specific inserter which may returns a new basic block.
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MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
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InsertPos = MBB->end();
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} else {
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MBB->insert(InsertPos, MI);
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}
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// Additional results must be an physical register def.
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if (HasPhysRegOuts) {
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for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
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unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
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if (Node->hasAnyUseOfValue(i))
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EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
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// If there are no uses, mark the register as dead now, so that
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// MachineLICM/Sink can see that it's dead. Don't do this if the
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// node has a Flag value, for the benefit of targets still using
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// Flag for values in physregs.
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else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
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MI->addRegisterDead(Reg, TRI);
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}
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}
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return;
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}
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/// EmitSpecialNode - Generate machine code for a target-independent node and
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/// needed dependencies.
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void InstrEmitter::
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EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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switch (Node->getOpcode()) {
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default:
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#ifndef NDEBUG
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@ -113,7 +113,12 @@ public:
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///
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void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
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if (Node->isMachineOpcode())
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EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap, EM);
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else
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EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap, EM);
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}
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/// getBlock - Return the current basic block.
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MachineBasicBlock *getBlock() { return MBB; }
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@ -124,6 +129,14 @@ public:
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/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
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/// at the given position in the given block.
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InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos);
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private:
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void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
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void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM);
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};
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}
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